公开(公告)号：US06901343B2

公开(公告)日：2005-05-31

申请号：US10029571

申请日：2001-12-20

申请人： Eiji Takahashi ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Osamu Shibata ,  Shinichi Tanimoto ,  Takeshi Nakayama

发明人： Eiji Takahashi ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Osamu Shibata ,  Shinichi Tanimoto ,  Takeshi Nakayama

IPC分类号： G06F17/50 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H04L9/32

CPC分类号： G06F17/5068 ,  H05K1/0275 ,  H05K1/0298 ,  H05K1/114 ,  H05K2201/09627 ,  H05K2201/09772 ,  H05K2201/10151

摘要： A signal line, being in a six-layer board and connecting terminal 102 of component 101 with terminal 115 of component 114, requires tamper-resistance. The signal line is composed of foil 103 on an outside layer, a via 104, foil 111 on the third layer, via 105, foil 112 on the fourth layer, via 106, and foil 113 on the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foil 103 and an end of via 104 are placed under component 101 on first layer 116, an end of via 105 is placed under component 107 on layer 116, an end of via 106 is placed under component 108 on layer 116, the other end of via 104 is placed under component 109 on sixth layer 121, the other end of via 105 is placed under component 110 on layer 121, and foil 113 and the other end of via 106 are placed under component 114 on layer 121.

摘要翻译： 在组件101的六层板和连接端子102与元件114的端子115之间的信号线需要防篡改。 信号线由外层的箔103，通孔104，第三层上的箔111，通孔105，第四层上的箔112，第106层和第六层上的箔113组成。 存在于外层的信号线部分都隐藏在电路元件下面。 箔103和通孔104的末端放置在第一层116上的部件101下方，通孔105的端部放置在层116上的部件107的下方，通孔106的端部放置在层116上的部件108的下方，另一端 通孔104被放置在第六层121上的部件109的下方，通孔105的另一端被放置在层121上的部件110下方，并且箔113和通孔106的另一端放置在层121上的部件114下方。

公开(公告)号：US06629302B2

公开(公告)日：2003-09-30

申请号：US09746886

申请日：2000-12-22

申请人： Shinji Miura ,  Yukihiro Fukumoto ,  Hirokazu Uemura ,  Yoshiyuki Saito ,  Hiroshi Ikeda ,  Takeshi Nakayama ,  Osamu Shibata ,  Shinichi Tanimoto

发明人： Shinji Miura ,  Yukihiro Fukumoto ,  Hirokazu Uemura ,  Yoshiyuki Saito ,  Hiroshi Ikeda ,  Takeshi Nakayama ,  Osamu Shibata ,  Shinichi Tanimoto

IPC分类号： G06F945

CPC分类号： G06F17/5068

摘要： A design aiding apparatus and a method, and a storage medium storing a design aiding program enable the efficient layout design of components in a multilayer wiring board formed by laminating a plurality of wiring layers. The design aiding apparatus includes (a) a first acquiring unit for acquiring information showing a first location in a lamination direction of the wiring layers, (b) a second acquiring unit for acquiring information showing a second location on a two-dimensional plane that is orthogonal to the lamination direction, and (c) a placement unit for generating information showing a space to be occupied when the component is placed in such a manner that a placement reference point of the component coincides with the second location that is on the two-dimensional plane including the first location. According to the above construction, the present invention is capable of aiding layout design of components in the wiring board.

摘要翻译： 设计辅助装置和方法以及存储设计辅助程序的存储介质使得能够通过层叠多个布线层而形成的多层布线板中的部件的有效布局设计。 设计辅助装置包括：（a）第一获取单元，用于获取表示布线层的层叠方向上的第一位置的信息，（b）第二获取单元，用于获取表示二维平面上的第二位置的信息， 与所述层叠方向正交，以及（c）放置单元，用于产生表示当所述部件以所述部件的放置基准点与所述第二位置的所述第二位置一致的方式配置时要占据的空间的信息， 包括第一位置的三维平面。 根据上述结构，本发明能够帮助布线板中部件的布局设计。

公开(公告)号：US5602778A

公开(公告)日：1997-02-11

申请号：US468393

申请日：1995-06-06

申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C11/34

CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

公开(公告)号：US5347490A

公开(公告)日：1994-09-13

申请号：US711532

申请日：1991-06-10

申请人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi

发明人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/02 ,  G11C16/16 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  G11C11/34

CPC分类号： G11C5/147 ,  G11C16/16 ,  G11C16/30

摘要： Disclosed is a flash EEPROM including a voltage lowering circuit therein for lowering an externally applied high voltage serving as a source of an erase pulse to a predetermined voltage in a range in which a tunnel phenomenon sufficiently occurs in memory cells. The voltage lowered by the voltage lowering circuit is converted into a pulse of a small width, and the converted pulse is then applied as an erase pulse to the memory cells. A flash EEPROM including a memory cell array divided into first and second blocks is also disclosed. An erase pulse applying circuit for applying the voltage lowered by the voltage lowering circuit as an erase pulse to the memory cells, and an erase verify circuit for erase verifying are provided for each of the first and second blocks. The erase pulse applying circuit and the erase verify circuit corresponding to the first block and the ones corresponding to the second block are configured to operate independently.

摘要翻译： 公开了一种闪速EEPROM，其包括其中在存储单元中充分发生隧道现象的范围内将用作擦除脉冲源的外部施加的高电压降低到预定电压的电压降低电路。 由降压电路降低的电压被转换为宽度较小的脉冲，然后将转换的脉冲作为擦除脉冲施加到存储单元。 还公开了一种包括分为第一和第二块的存储单元阵列的闪存EEPROM。 提供了用于将由降压电路降低的电压作为擦除脉冲施加到存储单元的擦除脉冲施加电路，以及用于擦除验证的擦除验证电路用于第一和第二块中的每一个。 擦除脉冲施加电路和对应于第一块的擦除验证电路和对应于第二块的擦除验证电路被配置为独立地操作。

公开(公告)号：US5146345A

公开(公告)日：1992-09-08

申请号：US784535

申请日：1991-10-29

申请人： Atsushi Yamashita ,  Takeshi Nakayama

发明人： Atsushi Yamashita ,  Takeshi Nakayama

IPC分类号： B43L1/04 ,  H04N1/00

CPC分类号： H04N1/00525 ,  H04N2201/0096

摘要： A foldable electronic print board copies or records, on recording paper, various patterns of information, including letters, numerals, images, etc., which have been handwritten on a writing sheet. The foldable electronic print board has a pair of hinged cases housing the writing sheet, and a printer for printing the handwritten information on the recording paper. The printer is detachably mounted on the cases across the axis about which the print board is foldable, to keep the print board unfolded. Since the printer itself is used to hold the print board unfolded, no dedicated holder or holders are required to be fixed to the cases. The printer is located at the geometric center of the print board for thereby making the print board stable in use.

摘要翻译： 可折叠电子印刷电路板在记录纸上复制或记录在书写纸上手写的各种信息模式，包括字母，数字，图像等。 可折叠电子印刷电路板具有容纳写字纸的一对铰链盒，以及用于将手写信息打印在记录纸上的打印机。 打印机可拆卸地安装在穿过打印板可折叠的轴线的壳体上，以保持打印板展开。 由于打印机本身用于固定打印板展开，所以不需要专门的固定器或固定器来固定。 打印机位于打印板的几何中心，从而使打印板在使用中稳定。

公开(公告)号：US5112148A

公开(公告)日：1992-05-12

申请号：US640570

申请日：1991-01-14

申请人： Koki Tanaka ,  Yoshikazu Heshiki ,  Takeshi Nakayama

发明人： Koki Tanaka ,  Yoshikazu Heshiki ,  Takeshi Nakayama

IPC分类号： G06F17/27

CPC分类号： G06F17/273

摘要： An electronic typewriter comprises a printing head, a carriage on which the printing head is movable along along a printing line, a keyboard including various keys, a carriage pointer for indicating the position at which the carriage is presently located, a line buffer having sequential memory locations corresponding to printing positions on the printing line, and a control circuit for performing a character key processing when a character key is operated and a space key processing when a space key is operated. In the electronic typewriter, the control means is constructed so as to perform a carriage return processing when a carriage return key is operated, in which processing the spelling of such a word is checked that one of the characteristic codes forming the word or a space code following the word is stored in a memory location of said line buffer specified by the carriage pointer, the carriage and carriage pointer are retuned to a predetermined home position thereafter, and the returning of carriage and carriage pointer is omitted when an error is detected in the spelling check.

摘要翻译： 电子打字机包括打印头，打印头沿着打印线可移动的托架，包括各种键的键盘，用于指示托架当前所在的位置的托架指针，具有顺序存储器的行缓冲器 与打印行上的打印位置对应的位置，以及用于当操作字符键时执行字符键处理的控制电路，以及当操作空格键时的空格键处理。 在电子打字机中，控制装置被构造成当操作回车键时执行回车处理，其中检查这样一个字的拼写检查形成该单词的特征码或空格码之一 在单词被存储在由滑架指针指定的所述行缓冲器的存储器位置中之后，托架和托架指针将被重新保留到预定的原始位置，并且当检测到错误时，省略托架和托架指针的返回 拼写检查。

公开(公告)号：US4970727A

公开(公告)日：1990-11-13

申请号：US263118

申请日：1988-10-27

申请人： Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Takeshi Nakayama ,  Kazuo Kobayashi ,  Yasushi Terada

发明人： Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Takeshi Nakayama ,  Kazuo Kobayashi ,  Yasushi Terada

IPC分类号： G11C11/401 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G11C16/02 ,  G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： In a semiconductor integrated circuit such as a semiconductor memory device capable of operating in a special mode in addition to a standard operation mode, a high voltage detection circuit 10 detects a high voltage applied to one of control signal input terminals CS and outputs a detection signal HV to a special mode circuit 14. The special mode circuit 14 outputs a switch signal CO to a switching circuit 11 in response to the detection signal HV. The switching circuit 11 connects an input/output buffer 7 to a latch circuit 12 in response to the switch signal CO. A special mode code MC is applied to input/output terminals DT and transmitted to the latch circuit 12 through the switching circuit 11. A special mode decoder 13 decodes the special mode code MC which has been latched by the latch circuit 12 and outputs a signal for specifying the special mode to a control circuit 8. Operation in the special mode specified by the control circuit 8 is executed. By detecting a confirmation signal CS applied to one of the control signal input terminals CS during the execution of the special mode, the special mode code MC which has been already latched by the latch circuit 12 can be outputted from the input/output terminals DT.

摘要翻译： 在除了标准工作模式之外能够以特殊模式工作的半导体存储器件的半导体集成电路中，高电压检测电路10检测施加到控制信号输入端子CS之一的高电压，并输出检测信号 HV到特殊模式电路14.特殊模式电路14响应于检测信号HV将开关信号CO输出到开关电路11。 开关电路11响应于开关信号CO将输入/输出缓冲器7连接到锁存电路12.特殊模式代码MC被施加到输入/输出端子DT，并通过开关电路11发送到锁存电路12。 特殊模式解码器13解码由锁存电路12锁存的特殊模式代码MC，并将用于指定特殊模式的信号输出到控制电路8.执行由控制电路8指定的特殊模式中的操作。 通过检测在特殊模式执行期间施加到控制信号输入端子CS之一的确认信号CS，可以从输入/输出端子DT输出已被锁存电路12锁存的特殊模式代码MC。

公开(公告)号：US4933906A

公开(公告)日：1990-06-12

申请号：US288791

申请日：1988-11-18

申请人： Yasushi Terada ,  Takeshi Nakayama ,  Kazuo Kobayashi

发明人： Yasushi Terada ,  Takeshi Nakayama ,  Kazuo Kobayashi

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/28

CPC分类号： G11C16/28

摘要： A semiconductor memory device of erasable programmable rear only memory type is disclosed the memory device has a pair of memory cell arrays between which a differential amplifier is provided. Each of the memory cell arrays has a current-to-voltage converter circuit associated therewith. When a memory cell in either one of the pair of memory cell array is selected, a bit line being coupled to the selected memory cell is charged by one current-voltage conversion circuit, while at the same time at least one bit line in the other memory cell array where no memory cell has been selected is charged by the associated current-voltage converter circuit at arrayed different from the bit line coupled to the selected memory cell. A differential amplifier senses and amplifies a potential difference between the charged bit lines to provide a high speed read-out of the memory device.

摘要翻译： 公开了一种可擦除可编程后唯一存储器类型的半导体存储器件，该存储器件具有一对存储单元阵列，在该存储单元阵列之间提供差分放大器。 每个存储单元阵列具有与其相关联的电流 - 电压转换器电路。 当选择一对存储单元阵列中的任何一个中的存储单元时，耦合到所选存储单元的位线由一个电流 - 电压转换电路充电，而在另一个存储单元阵列中同时至少有一个位线 没有选择存储器单元的存储单元阵列被相关联的电流 - 电压转换器电路充电，该电流 - 电压转换器电路阵列地与耦合到所选存储单元的位线不同。 差分放大器感测并放大充电位线之间的电位差，以提供存储器件的高速读出。

公开(公告)号：US4858194A

公开(公告)日：1989-08-15

申请号：US154573

申请日：1988-02-10

申请人： Yasushi Terada ,  Takeshi Nakayama ,  Kazuo Kobayashi

发明人： Yasushi Terada ,  Takeshi Nakayama ,  Kazuo Kobayashi

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24

CPC分类号： G11C16/24 ,  G11C16/08 ,  G11C16/12

摘要： A nonvolatile semiconductor memory device comprises memory cells each formed of a single memory transistor and can be accessed in a bit-by-bit manner to eliminate an erase cycle in a data write cycle. The memory device comprises precharging circuits for precharging word lines and bit lines in the data write cycle, tri-level V.sub.pp switches, in response to a data to be written and an output of X decoder, for applying to a selected word line a write voltage V.sub.pp when the data to be written is "1" while a ground potential when the data to be written is "0", and further applying remaining non-selected word lines the precharge voltage, and tri-level V.sub.pp switches, in response to a data to be written and an output of Y decoder, for applying to a selected bit line the ground potential when the data to be written is "1" while the write high-voltage V.sub.pp when the data to be written is "0", and further to the remaining non-selected bit lines the precharge voltage.

摘要翻译： 非易失性半导体存储器件包括由单个存储晶体管形成的存储单元，并且可以逐位访问以消除数据写周期中的擦除周期。 存储器件包括用于在数据写入周期中预充电字线和位线的预充电电路，响应于要写入的数据和X解码器的输出的三电平Vpp开关，用于向所选择的字线施加写入电压 当要写入的数据为“0”时要写入的数据为“1”，而要写入的数据为“0”时的接地电位，并且还应用剩余的未选择字线的预充电电压和三电平Vpp来响应于 要写入的数据和Y解码器的输出，当要写入的数据为“1”时，当要写入的数据为“0”时，将要写入的数据为“1”时，向选定的位线施加地电位，而当写入数据为“0”时，写入高电压Vpp， 进一步到剩余的未选择位线的预充电电压。

公开(公告)号：US4811294A

公开(公告)日：1989-03-07

申请号：US876914

申请日：1986-06-20

申请人： Kazuo Kobayashi ,  Takeshi Nakayama ,  Yasushi Terada

发明人： Kazuo Kobayashi ,  Takeshi Nakayama ,  Yasushi Terada

IPC分类号： G11C17/00 ,  G06F12/16 ,  G11C16/02 ,  G11C16/34 ,  G11C29/04 ,  G11C29/52 ,  G11B7/00

CPC分类号： G11C16/3445 ,  G11C16/3436 ,  G11C16/3459 ,  G11C29/04 ,  G11C29/52

摘要： An EEPROM provided with a write/erase checking circuit comprising, a data detector for determining whether one byte in an input data contains a "0" (representing that a memory cell is not in an erase state); an address latch circuit and a data latch circuit which latch the address and the input data, respectively, responsive to a detection signal from the data detector; a data read circuit which selects the memory cells according to the address stored in the address latch circuit and reads the data out of the memory cells at the data write checking; and a comparator which compares the data from the data read circuit with the data stored in the data latch circuit.

摘要翻译： 具有写入/擦除检查电路的EEPROM包括：数据检测器，用于确定输入数据中的一个字节是否包含“0”（表示存储器单元不处于擦除状态）; 地址锁存电路和数据锁存电路，分别根据来自数据检测器的检测信号来锁存地址和输入数据; 数据读取电路，根据存储在地址锁存电路中的地址选择存储单元，并在数据写入检查时从存储器单元读出数据; 以及将来自数据读取电路的数据与存储在数据锁存电路中的数据进行比较的比较器。