公开(公告)号：US20210118943A1

公开(公告)日：2021-04-22

申请号：US17113045

申请日：2020-12-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L27/15 ,  H01L25/075 ,  H01L33/38 ,  H01L33/62

Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including at least one LED driving circuit; a second single crystal layer including a first plurality of light emitting diodes (LEDs), where the second single crystal layer includes at least ten individual first LED pixels; and a second plurality of light emitting diodes (LEDs), where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm, and where the 3D micro display includes an oxide to oxide bonding structure.

公开(公告)号：US20200350310A1

公开(公告)日：2020-11-05

申请号：US16936352

申请日：2020-07-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L27/06 ,  G03F9/00 ,  H01L21/762 ,  H01L21/84 ,  H01L23/48 ,  H01L23/544 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/812 ,  H01L29/423 ,  H01L29/732 ,  H01L29/808 ,  H01L21/768 ,  H01L21/822 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.

公开(公告)号：US20200335399A1

公开(公告)日：2020-10-22

申请号：US16916103

申请日：2020-06-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L27/105 ,  H01L21/683 ,  H01L23/525 ,  H01L21/84 ,  H03K19/17704 ,  H01L25/065 ,  H01L27/11 ,  H01L27/06 ,  H01L27/112 ,  G11C29/00 ,  H01L27/108 ,  H01L21/762 ,  H01L27/02 ,  H03K19/17764 ,  H01L23/544 ,  G11C16/04 ,  H01L29/78 ,  G11C17/14 ,  H03K17/687 ,  H01L25/18 ,  H03K19/17796 ,  H01L27/118 ,  G11C17/06 ,  H03K19/0948 ,  H01L29/786 ,  H01L27/092 ,  H01L23/36 ,  H03K19/17756 ,  H01L21/8238 ,  H01L27/11526 ,  G11C16/12 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/24 ,  H01L27/12 ,  G11C13/00

Abstract: A 3D semiconductor device including: a first level including first single crystal silicon and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors; a second level on top of the first metal layer, the second level including a plurality of second transistors; a third level on top of the second level, the third level including a plurality of third transistors; an oxide layer on top of the third level; a fourth level on top of the oxide layer, the fourth level including second single crystal silicon and many fourth transistors, where at least one of the plurality of second transistors is at least partially self-aligned to at least one of the plurality of third transistors, both being formed following the same lithography step, the fourth level is bonded to the oxide layer, the bonded includes many metal to metal bonded structures.

公开(公告)号：US20190273121A1

公开(公告)日：2019-09-05

申请号：US16409813

申请日：2019-05-11

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L27/24 ,  H01L29/423 ,  H01L27/22 ,  H01L27/108 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L29/78 ,  H01L27/12 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11529

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.

公开(公告)号：US10388863B2

公开(公告)日：2019-08-20

申请号：US15452615

申请日：2017-03-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/108 ,  H01L21/762 ,  H01L27/06 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/00

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.

公开(公告)号：US10325651B2

公开(公告)日：2019-06-18

申请号：US15494525

申请日：2017-04-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G11C13/00 ,  H01L27/24 ,  G11C29/00 ,  H01L45/00 ,  G11C11/404 ,  G11C11/4097 ,  H01L29/78 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11578 ,  H01L49/02 ,  G11C11/412 ,  G11C16/04

Abstract: A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.

公开(公告)号：US20190164834A1

公开(公告)日：2019-05-30

申请号：US16246412

申请日：2019-01-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L21/8238 ,  H03K19/177 ,  G11C16/04 ,  H01L27/105 ,  H01L29/78 ,  G11C17/14 ,  H01L21/683 ,  H01L27/108 ,  H01L23/525 ,  H01L21/84 ,  H03K17/687 ,  H01L25/18 ,  H01L25/065 ,  H01L27/11 ,  H01L27/112 ,  H01L27/118 ,  G11C17/06 ,  H01L27/06 ,  H03K19/0948 ,  H01L29/786 ,  H01L27/092 ,  H01L23/36 ,  G11C29/00 ,  H01L21/762 ,  H01L27/02 ,  H01L23/544

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells includes one first transistor, where each of the second memory cells includes one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, and where the forming at least one third level includes forming a window within the third level so to allow a lithography alignment through the third level to an alignment mark disposed underneath the third level.

公开(公告)号：US20190067110A1

公开(公告)日：2019-02-28

申请号：US16171036

申请日：2018-10-25

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L21/8238

Abstract: A 3D semiconductor device including: a first level with first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact plugs provide connections from the first transistors to the first metal, where connections formed logic circuits; a second level with second transistors; a third level with third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level, second level includes first memory cells where each of the memory cells include at least one of the second transistors; and vertically oriented conductive plugs, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, where one end of each of the vertically oriented conductive plugs are connected to the second metal layer, where at least one of the vertically oriented conductive plugs is disposed directly on one of the contact plugs.

公开(公告)号：US20190006240A1

公开(公告)日：2019-01-03

申请号：US16101438

申请日：2018-08-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L29/786 ,  H01L29/78 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/683 ,  G11C29/00 ,  G11C17/14 ,  G11C17/06 ,  G11C16/04 ,  H01L23/48 ,  H01L23/00

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors underlying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell underlying the memory peripheral circuits; a second memory cell underlying the first memory cell, and a non-volatile NAND memory, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type, here the non-volatile NAND memory includes the first memory cell, and where at least one of the second transistors includes a polysilicon channel.

公开(公告)号：US09954080B2

公开(公告)日：2018-04-24

申请号：US15622124

申请日：2017-06-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00 ,  H01L29/66 ,  H01L23/544 ,  H01L27/02 ,  H01L27/088 ,  H01L21/74 ,  H01L27/11551 ,  H01L29/78 ,  H01L23/34 ,  H01L27/11573 ,  H01L23/50 ,  H01L27/11526 ,  H01L23/48 ,  H01L27/118 ,  H01L29/10 ,  H01L27/108 ,  H01L29/732 ,  H01L27/11578 ,  H01L29/808 ,  H01L27/06 ,  H01L27/24

CPC classification number: H01L29/66704 ,  H01L21/743 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/786 ,  H01L29/808 ,  H01L45/04 ,  H01L45/06 ,  H01L45/146 ,  H01L45/16 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment.