公开(公告)号：US09496359B2

公开(公告)日：2016-11-15

申请号：US13427062

申请日：2012-03-22

申请人： Brian K. Kirkpatrick ,  Amitabh Jain

发明人： Brian K. Kirkpatrick ,  Amitabh Jain

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/778

CPC分类号： H01L27/092 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823864 ,  H01L29/161 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/778 ,  H01L29/7833

摘要： A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

摘要翻译： 一种制造集成电路的方法包括：将第一电介质材料沉积在其上具有栅极堆叠的衬底的半导体表面上，其中栅极堆叠包括在栅极电介质上的栅电极。 蚀刻第一电介质材料以在栅叠层的侧壁上形成侧壁间隔物。 通过添加至少一个元件以提供表面转换的侧壁间隔物，将第一介电材料的顶表面化学转化为第二介电材料。 第二电介质材料通过过渡区化学键合到第一介电材料。

公开(公告)号：US20100261353A1

公开(公告)日：2010-10-14

申请号：US12757665

申请日：2010-04-09

申请人： Steven L. Prins ,  Brian K. Kirkpatrick ,  Amitabh Jain

发明人： Steven L. Prins ,  Brian K. Kirkpatrick ,  Amitabh Jain

IPC分类号： H01L21/465 ,  H01L21/46

CPC分类号： H01L22/20 ,  G03F7/70616 ,  G03F7/70783 ,  G03F7/70875 ,  H01L22/12

摘要： A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.

摘要翻译： 一种用于在光刻图案级别之间控制晶片的平坦度的方法。 在晶片的顶侧半导体表面上进行第一光刻步骤。 获得晶片的参考曲率信息。 参考曲率不是平面的。 执行至少一个处理步骤，其导致相对于参考曲率改变的曲率。 获得用于晶片的变化的曲率信息。 修改了晶片底部表面上的应力，减小了改变的曲率和参考曲率之间的差异。 在存在改性应力分布的同时，在顶侧半导体表面上进行第二光刻步骤。

公开(公告)号：US20100133624A1

公开(公告)日：2010-06-03

申请号：US12696215

申请日：2010-01-29

申请人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

发明人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

摘要翻译： 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US07557022B2

公开(公告)日：2009-07-07

申请号：US11451919

申请日：2006-06-13

申请人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

发明人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

IPC分类号： H01L21/425

CPC分类号： H01L21/2658 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.

摘要翻译： 公开了一种NMOS晶体管的形成，其中碳，原子氟和分子氟（F2）中的至少一种与砷，磷和锑中的至少一种的注入组合。 掺杂剂组合可用于LDD注入以形成源极/漏极延伸区域，以及用于形成卤素区域和/或源极/漏极区域的注入。 掺杂剂的组合有助于降低薄层电阻并增加载流子迁移率，这进而有助于器件缩放和期望的器件性能。

公开(公告)号：US20090047768A1

公开(公告)日：2009-02-19

申请号：US12190337

申请日：2008-08-12

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/2251 ,  H01L21/2255 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833

摘要： A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm−2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.

摘要翻译： 公开了一种用于在IC衬底，特别是MOS晶体管中的LDD区域形成平均掺杂剂量高于1014cm -2的深度小于20nm的扩散区域的工艺。 使用气体簇离子束（GCIB）注入，分子离子注入或原子离子注入将掺杂剂注入到源电介质层中，导致IC衬底中的可忽略的损伤。 尖峰退火或激光退火将注入的掺杂剂扩散到IC衬底中。 本发明的方法也可以应用于形成源极和漏极（S / D）区域。 一个源介质层可用于形成NLDD和PLDD区域。

公开(公告)号：US07344985B2

公开(公告)日：2008-03-18

申请号：US11551374

申请日：2006-10-20

申请人： Peijun J. Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas D. Bonifield ,  Homi Mogul

发明人： Peijun J. Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas D. Bonifield ,  Homi Mogul

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

摘要翻译： 本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。 除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。 该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

公开(公告)号：US20070218662A1

公开(公告)日：2007-09-20

申请号：US11725927

申请日：2007-03-20

申请人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

发明人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

IPC分类号： H01L21/425

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/7833

摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.

摘要翻译： 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻，同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

公开(公告)号：US07173296B2

公开(公告)日：2007-02-06

申请号：US10959689

申请日：2004-10-06

申请人： Haowen Bu ,  Clinton L. Montgomery ,  Amitabh Jain

发明人： Haowen Bu ,  Clinton L. Montgomery ,  Amitabh Jain

IPC分类号： H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/3145 ,  H01L21/31612 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

摘要翻译： 本发明的一个实施例是制造半导体结构10的方法，其中通过无氢前体CVD工艺形成间隔氧化物层90。 本发明的另一实施例是具有氢含量小于1％的间隔氧化物层90的半导体结构10。

公开(公告)号：US20070020900A1

公开(公告)日：2007-01-25

申请号：US11175682

申请日：2005-07-06

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/3205

CPC分类号： H01L21/2807

摘要： The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode to allow the dopant to diffuse throughout the gate electrode. The method further comprises re-solidifying the gate electrode to increase dopant-occupied substitutional sites within the gate electrode.

摘要翻译： 在一个实施例中，本发明提供了一种用于制造微电子器件的方法。 该方法包括将掺杂剂注入到位于衬底上的栅电极中。 栅电极的熔点低于基板的熔点。 该方法还包括熔化栅电极以允许掺杂剂在整个栅电极中扩散。 该方法还包括重新固化栅电极以增加栅电极内的掺杂剂占据的取代位置。

公开(公告)号：US20060199346A1

公开(公告)日：2006-09-07

申请号：US11379426

申请日：2006-04-20

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

摘要翻译： 一种在半导体晶片内制造晶体管的方法。 该方法可以包括蚀刻源极/漏极扩展位置90处的凹陷并在凹槽内沉积SiGe以形成SiGe源极/漏极延伸部90.掺杂剂注入到SiGe源极/漏极延伸部分90中并且半导体晶片10被退火。 此外，具有含有均匀分布的掺杂剂的SiGe源极/漏极延伸部90的晶体管源极/漏极区域80,90是高度掺杂的，并且具有高度突变的边缘。