Abstract:
A magnetoresistive random access memory (MRAM) and associated apparatus and methods are described. The MRAM generally includes a heavy metal layer coupled to a source line, and a plurality of bit cells coupled to a word line, a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines.
Abstract:
In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.
Abstract:
A material stack of a synthetic anti-ferromagnetic (SAF) reference layer of a perpendicular magnetic tunnel junction (MTJ) may include an SAF coupling layer. The material stack may also include and an amorphous spacer layer on the SAF coupling layer. The amorphous spacer layer may include an alloy or multilayer of tantalum and cobalt or tantalum and iron or cobalt and iron and tantalum. The amorphous spacer layer may also include a treated surface of the SAF coupling layer.
Abstract:
An apparatus includes a capping layer disposed on top of a free layer. The apparatus also includes a magnetic etch stop layer disposed on top of the capping layer. The capping layer and the magnetic etch stop layer are included in a spin-transfer torque magnetoresistive random access memory (STT-MRAM) magnetic tunnel junction (MTJ) device.
Abstract:
A magnetic tunnel junction (MTJ) and methods for fabricating a MTJ are described. An MTJ includes a fixed layer and a barrier layer on the fixed layer. Such an MTJ also includes a free layer interfacing with the barrier layer. The free layer has a crystal structure in accordance with the barrier layer. The MTJ further includes an amorphous capping layer interfacing with the free layer.
Abstract:
Perpendicular magnetic tunnel junction (pMTJ) devices employing a pinned layer stack with a thin top anti-parallel (AP2) layer and having a transitioning layer providing a transitioning start to a body-centered cubic (BCC) crystalline/amorphous structure below the top anti-parallel (AP2) layer, to promote a high tunnel magnetoresistance ratio (TMR) with reduced pinned layer thickness are disclosed. A first anti-parallel (AP) ferromagnetic (AP1) layer in a pinned layer has a face-centered cubic (FCC) or hexagonal closed packed (HCP) crystalline structure. A transitioning material (e.g., Iron (Fe)) is provided in a transitioning layer between the AP1 layer and an AFC layer (e.g., Chromium (Cr)) that starts a transition from a FCC or HCP crystalline structure, to a BCC crystalline/amorphous structure. In this manner, a second AP ferromagnetic (AP2) layer disposed on the AFC layer can be provided in a reduced thickness BCC crystalline or amorphous structure to provide a high TMR with a reduced pinned layer thickness.
Abstract:
Magnetic tunnel junction (MTJ) memory bit cells that decouple source line layout from access transistor node size to facilitate reduced contact resistance are disclosed. In one example, an MTJ memory bit cell is provided that includes a source plate disposed above and in contact with a source contact for a source node of an access transistor. A source line is disposed above and in electrical contact with the source plate to electrically connect the source line to the source node. The source plate allows the source line to be provided in a higher metal level from the source and drain contacts of the access transistor such that the source line is not in physical contact with (i.e., decoupled from) the source contact. This allows pitch between the source line and drain column to be relaxed from the width of the source and drain nodes without having to increase contact resistance.
Abstract:
A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.
Abstract:
A method for fabricating a perpendicular magnetic tunnel junction (pMTJ) device includes growing a seed layer on a first electrode of the pMTJ device. The seed layer has a uniform predetermined crystal orientation along a growth axis. The method also includes planarizing the seed layer while maintaining the uniform predetermined crystal orientation of the seed layer.
Abstract:
An apparatus includes a capping layer disposed on top of a free layer. The apparatus also includes a magnetic etch stop layer disposed on top of the capping layer. The capping layer and the magnetic etch stop layer are included in a spin-transfer torque magnetoresistive random access memory (STT-MRAM) magnetic tunnel junction (MTJ) device.