公开(公告)号：US08332619B2

公开(公告)日：2012-12-11

申请号：US13314826

申请日：2011-12-08

Applicant: Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

Inventor： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC classification number: G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

Abstract translation: 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US08019947B2

公开(公告)日：2011-09-13

申请号：US11254286

申请日：2005-10-19

Applicant: Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Per Hammarlund

Inventor： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Per Hammarlund

IPC: G06F12/00

CPC classification number: G06F9/542 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F12/0831 ,  G06F2209/543

Abstract: A technique for thread synchronization and communication. More particularly, embodiments of the invention pertain to managing communication and synchronization among two or more threads of instructions being executing by one or more microprocessors or microprocessor cores.

Abstract translation: 一种用于线程同步和通信的技术。 更具体地，本发明的实施例涉及管理由一个或多个微处理器或微处理器核执行的两个或多个指令线程之间的通信和同步。

公开(公告)号：US20100191993A1

公开(公告)日：2010-07-29

申请号：US12361422

申请日：2009-01-28

Applicant: Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

Inventor： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

IPC: G06F1/32 ,  G06F1/26 ,  G06F9/30

CPC classification number: G06F9/3867 ,  G06F1/206 ,  G06F1/3203 ,  G06F9/3869 ,  Y02D10/16

Abstract: A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.

Abstract translation: 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。

公开(公告)号：US07565511B2

公开(公告)日：2009-07-21

申请号：US11425869

申请日：2006-06-22

Applicant: Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

Inventor： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

IPC: G06F9/30

CPC classification number: G06F9/3867 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

Abstract: A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.

Abstract translation: 一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。 该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。

公开(公告)号：US07509481B2

公开(公告)日：2009-03-24

申请号：US11277735

申请日：2006-03-28

Applicant: Shailender Chaudhry ,  Paul Caprioli ,  Quinn A. Jacobson ,  Marc Tremblay

Inventor： Shailender Chaudhry ,  Paul Caprioli ,  Quinn A. Jacobson ,  Marc Tremblay

IPC: G06F9/00

CPC classification number: G06F9/30145 ,  G06F9/30174 ,  G06F9/30196 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3897

Abstract: Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.

Abstract translation: 已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。 特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。 例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。 可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。 类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。 在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。 在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。

公开(公告)号：US07490229B2

公开(公告)日：2009-02-10

申请号：US11093197

申请日：2005-03-29

Applicant: Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

Inventor： Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

IPC: G06F9/00

CPC classification number: G06F9/3844 ,  G06F9/30105 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

Abstract: One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same branches during non-speculative execution. During operation, the system executes code within a processor. Upon encountering a stall condition, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. Upon encountering a branch instruction that is resolved during speculative execution, the system stores the result of the resolved branch in a branch queue, so that the result can be subsequently used to predict the branch during non-speculative execution.

Abstract translation: 本发明的一个实施例提供一种便于在推测性执行期间存储可解析分支的结果的系统，然后在非推测性执行期间使用结果来预测相同的分支。 在操作期间，系统在处理器内执行代码。 在遇到停顿状态时，系统从失速点推测地执行代码，而不会将推测性执行的结果提交给处理器的体系结构状态。 在遇到在推测执行期间解析的分支指令时，系统将解析的分支的结果存储在分支队列中，以便随后可以在非推测性执行期间将结果用于预测分支。

公开(公告)号：US20080162816A1

公开(公告)日：2008-07-03

申请号：US11646642

申请日：2006-12-27

Applicant: Mark Buxton ,  Ernie Brickell ,  Quinn A. Jacobson ,  Hong Wang ,  Baiju Patel

Inventor： Mark Buxton ,  Ernie Brickell ,  Quinn A. Jacobson ,  Hong Wang ,  Baiju Patel

IPC: G06F12/08

CPC classification number: G06F12/0842 ,  G06F9/30047 ,  G06F12/1458 ,  G06F21/52 ,  G06F21/78

Abstract: For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.

Abstract translation: 对于与线程相关联的一组存储器位置中的每个存储器位置，设置与存储器位置相关联的指示，以便如果来自存储器位置的数据被从高速缓存中移出，则请求信号; 并且响应于该信号，将该组存储器位置重新加载到高速缓存中。

公开(公告)号：US20080005737A1

公开(公告)日：2008-01-03

申请号：US11480090

申请日：2006-06-30

Applicant: Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Quinn A. Jacobson

Inventor： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Quinn A. Jacobson

IPC: G06F9/46

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/3005 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F2209/521

Abstract: Various usage models are provided to utilize a Monitor and Call (“mcall”) instruction that incorporates user-level asynchronous signaling. The various usage models utilize the mcall instruction in a multithreading system in order to enhance concurrent thread execution. Other embodiments are also described and claimed.

Abstract translation: 提供了各种使用模型以利用包含用户级异步信令的监视和呼叫（“mcall”）指令。 各种使用模式在多线程系统中使用mcall指令，以增强并发线程执行。 还描述和要求保护其他实施例。

公开(公告)号：US07216202B1

公开(公告)日：2007-05-08

申请号：US10787386

申请日：2004-02-24

Applicant: Shailender Chaudhry ,  Marc Tremblay ,  Quinn A. Jacobson

Inventor： Shailender Chaudhry ,  Marc Tremblay ,  Quinn A. Jacobson

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/3005 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/528 ,  G06F12/0815 ,  G06F2212/507 ,  G06F2212/681

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract translation: 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

公开(公告)号：US08266633B1

公开(公告)日：2012-09-11

申请号：US12069800

申请日：2008-02-12

Applicant: Ashley Saulsbury ,  Quinn A. Jacobson

Inventor： Ashley Saulsbury ,  Quinn A. Jacobson

IPC: G06F15/163

CPC classification number: G06F9/545 ,  G06F9/45558 ,  G06F9/546 ,  G06F2209/548

Abstract: A computer-based method configures a hardware circuit to transfer a message to a message queue in an operating system. The hardware circuit is used to transfer a message to the message queue in the operating system without requiring use of either the operating system or a hypervisor associated with the operating system. The configuring includes tieing (i) a value in a head pointer register with a head pointer for the message queue stored in the hardware circuit and (ii) a value in a tail pointer register for the message queue with a tail pointer for the message queue stored in the hardware circuit so that the value in the head pointer register equals the stored head pointer and the value in the tail pointer register equals the stored tail pointer. The using the hardware circuit uses a logical identifier associated with the message to select an entry in a mapping table of the hardware circuit. A value in the entry in the mapping table is used to select an entry in an action table. The entry in the action table is used to determine a tail pointer for the message queue. The hardware circuit appends the message to a location indicted by the tail pointer without requiring cycles of a hypervisor associated with the strand.

Abstract translation: 基于计算机的方法配置硬件电路以将消息传送到操作系统中的消息队列。 硬件电路用于将消息传送到操作系统中的消息队列，而不需要使用操作系统或与操作系统相关联的管理程序。 配置包括（i）头指针寄存器中的值与存储在硬件电路中的消息队列的头指针相关联，以及（ii）用于消息队列的尾指针寄存器中的值，其具有用于消息队列的尾指针 存储在硬件电路中，使得头指针寄存器中的值等于存储的头指针，并且尾指针寄存器中的值等于存储的尾指针。 使用硬件电路使用与消息相关联的逻辑标识符来选择硬件电路的映射表中的条目。 映射表中的条目中的值用于在操作表中选择一个条目。 动作表中的条目用于确定消息队列的尾部指针。 硬件电路将消息附加到由尾部指针指示的位置，而不需要与该线束相关联的管理程序的周期。