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112 条记录 (耗时 0.032 秒)

    Process of fabricating DRAM cells with collar isolation layers
    41.
    发明授权
    Process of fabricating DRAM cells with collar isolation layers 失效
    制造带有隔离层的DRAM单元的工艺

    公开(公告)号：US06797636B2

    公开(公告)日：2004-09-28

    申请号：US10157870

    申请日：2002-05-31

    申请人： Helmut Horst Tews ,  Rolf Weis

    发明人： Helmut Horst Tews ,  Rolf Weis

    IPC分类号： H01L21302

    CPC分类号： H01L27/1087 ,  H01L27/10864 ,  H01L27/1203

    摘要： A process of preparing DRAM cells with collar isolation layers that isolate the trench top with vertical cell and active area from the buried plate to eliminate the space normally required by a final collar, comprising: a) etching a deep trench (DT) in a substrate over which a patterned pad stack serving as a mask is positioned; b) depositing a silicon nitride sacrificial collar liner in a top art of the trench; c) etching below the sacrificial collar to form a bottle structure in a lower part of the trench; d) forming an oxide layer, a nitride layer over the oxide layer, depositing a resist fill, and affecting a recess of the resist fill to a recess depth below the top of the bottle formation; e) affecting a nitride etch followed by a resist strip f) affecting thermal oxidation using the nitride layer as a mask to form a closed layer of oxide at the top of the trench bottle shaped structure; g) affecting a nitride strip; and h) forming a buried plate by gas phase doping to cause isolation between the active area and the buried plate.

    摘要翻译： 一种制备具有轴环隔离层的DRAM单元的过程，其将沟槽顶部与垂直单元和有源区域与掩埋板隔离，以消除最终轴环通常所需的空间，包括：a）蚀刻衬底中的深沟槽（DT） 在其上定位用作掩模的图案化焊盘堆叠; b）在沟槽的顶部淀积氮化硅牺牲衬套; c）在牺牲衬套下方蚀刻以在沟槽的下部形成瓶结构; d）在所述氧化物层上形成氧化物层，氮化物层，沉积抗蚀剂填充物，并且将所述抗蚀剂填充物的凹陷影响到所述瓶形结构的顶部以下的凹陷深度; e）影响氮化物蚀刻，然后是抗蚀剂 使用氮化物层作为掩模影响热氧化，以在沟槽瓶形结构的顶部形成封闭的氧化物层; g）影响氮化物条带; 和h）通过气相掺杂形成掩埋板，以在有源区和掩埋板之间形成隔离。

    Self-aligned nitride pattern for improved process window
    42.
    发明授权
    Self-aligned nitride pattern for improved process window 失效

    公开(公告)号：US06576944B2

    公开(公告)日：2003-06-10

    申请号：US09736940

    申请日：2000-12-14

    申请人： Rolf Weis

    发明人： Rolf Weis

    IPC分类号： H01L2994

    CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10891

    摘要： A device and method for fabricating a gate structure are disclosed. A first conductive material is deposited in a trench formed in a substrate and the first conductive material is recessed to a level below a top surface of the substrate in the trench. A dielectric layer is conformally deposited in contact with the first conductive material in the trench and in contact with sidewalls of the trench. A hole is formed in the dielectric layer to expose the first conductive layer, and the hole is filled with a conductive material. A gate stack is formed over the trench such that an electrical connection is made to the first conductive layer in the trench by employing the conductive material through the dielectric layer.

    Semiconductor device and method for manufacturing a semiconductor device
    43.
    发明授权
    Semiconductor device and method for manufacturing a semiconductor device 有权

    公开(公告)号：US09685511B2

    公开(公告)日：2017-06-20

    申请号：US13476613

    申请日：2012-05-21

    申请人： Rolf Weis

    发明人： Rolf Weis

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

    CPC分类号： H01L29/1095 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

    摘要： A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches.

    Semiconductor Device and Method for Manufacturing a Semiconductor Device
    44.
    发明申请
    Semiconductor Device and Method for Manufacturing a Semiconductor Device 有权
    半导体装置及半导体装置的制造方法

    公开(公告)号：US20130307059A1

    公开(公告)日：2013-11-21

    申请号：US13476613

    申请日：2012-05-21

    申请人： Rolf Weis

    发明人： Rolf Weis

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/1095 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

    摘要： A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches.

    摘要翻译： 半导体器件包括第一导电类型的第一区域和第二导电类型的体区域，第一导电类型不同于第二导电类型。 身体区域设置在半导体衬底的第一表面的一侧。 半导体器件还包括布置在衬底的第一表面中的多个沟槽，沟槽沿着第一方向延伸，具有垂直于第一表面的分量。 第二导电类型的掺杂部分与沟槽的侧壁的下部相邻。 掺杂部分经由接触区电耦合到体区。 半导体器件还包括设置在沟槽上部的栅电极。

    Integrated Switching Device with Parallel Rectifier Element
    45.
    发明申请
    Integrated Switching Device with Parallel Rectifier Element 审中-公开
    具有并联整流元件的集成开关器件

    公开(公告)号：US20130264654A1

    公开(公告)日：2013-10-10

    申请号：US13441038

    申请日：2012-04-06

    申请人： Rolf Weis ,  Andreas Spitzer

    发明人： Rolf Weis ,  Andreas Spitzer

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0629 ,  H01L23/481 ,  H01L25/074 ,  H01L25/18 ,  H01L27/0688 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H03K17/102 ,  H01L2924/00

    摘要： An integrated circuit includes a semiconductor body with a first semiconductor layer and a second semiconductor layer arranged adjacent the first semiconductor layer in a vertical direction of the semiconductor body. The integrated circuit further includes a switching device with a control terminal and a load path between a first load terminal and a second load terminal, and a rectifier element connected in parallel with at least one section of the load path. The switching device is integrated in the first semiconductor layer and the rectifier element is integrated in the second semiconductor layer.

    摘要翻译： 集成电路包括具有第一半导体层的半导体本体和在半导体本体的垂直方向上与第一半导体层相邻布置的第二半导体层。 集成电路还包括具有控制端子和第一负载端子和第二负载端子之间的负载路径的开关装置，以及与负载路径的至少一个部分并联连接的整流元件。 开关器件集成在第一半导体层中，并且整流元件集成在第二半导体层中。

    Isolation trenches with conductive plates
    47.
    发明授权
    Isolation trenches with conductive plates 有权
    隔离槽与导电板

    公开(公告)号：US07795109B2

    公开(公告)日：2010-09-14

    申请号：US12144482

    申请日：2008-06-23

    申请人： Rolf Weis ,  Thomas D. Happ

    发明人： Rolf Weis ,  Thomas D. Happ

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224 ,  H01L27/2409 ,  H01L27/2445 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

    摘要： Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the channel. An insulating material is disposed in an upper portion of the recess over the conductive material.

    摘要翻译： 公开了形成隔离沟槽的方法，半导体器件，其结构以及操作存储器阵列的方法。 在一个实施例中，隔离沟槽包括设置在工件中的凹部。 导电材料设置在通道的下部。 绝缘材料设置在导电材料上的凹部的上部。

    Methods for generating sublithographic structures
    48.
    发明授权
    Methods for generating sublithographic structures 有权
    用于生成亚光刻结构的方法

    公开(公告)号：US07794614B2

    公开(公告)日：2010-09-14

    申请号：US11754813

    申请日：2007-05-29

    申请人： Rolf Weis ,  Christoph Noelscher

    发明人： Rolf Weis ,  Christoph Noelscher

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0334 ,  H01L21/28132 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  Y10S438/942 ,  Y10S438/947

    摘要： One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.

    摘要翻译： 一个可能的实施例是在以下步骤中在衬底上或衬底中制造结构的方法：a）通过间隔物技术将至少一个间隔物结构定位在衬底上，b）使用间隔结构的组中的至少一个和 由间隔结构生成的结构作为用于随后的用于在基板中产生潜像的颗粒照射步骤的掩模c）使用潜像进一步处理基板。

    Manufacturing method for an integrated semiconductor memory device and corresponding semiconductor memory device
    50.
    发明授权
    Manufacturing method for an integrated semiconductor memory device and corresponding semiconductor memory device 失效
    集成半导体存储器件和相应的半导体存储器件的制造方法

    公开(公告)号：US07605037B2

    公开(公告)日：2009-10-20

    申请号：US11704783

    申请日：2007-02-09

    申请人： Rolf Weis

    发明人： Rolf Weis

    IPC分类号： H01L21/336

    CPC分类号： G11C11/24 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： The present invention provides an integrated semiconductor memory device comprising: a semiconductor substrate; a plurality of active area lines formed in said semiconductor substrate, each of which active area lines includes a plurality of memory cell selection transistors having a respective wordline contact, bitline contact, and node contact; a plurality of filled insulation trenches arranged between said active area lines; a plurality of rewiring stripes each of which rewires an associated node contact of a memory cell selection transistor from an active area line to above a neighboring filled insulation trench so as to form a respective rewired node contact; a plurality of bitlines being aligned with and running above said active area lines which bitlines are connected to the bitline contacts of the memory cell selection transistors of the respective active area lines; a plurality of wordlines running perpendicular to said bitlines which are connected to the wordline contacts of the memory cell selection transistors of corresponding active area lines; and a plurality of memory cell capacitors each of which is connected to a respective rewired node contact of an associated memory cell selection transistor. The present invention also provides a corresponding manufacturing method for an integrated semiconductor memory device and a memory cell.

    摘要翻译： 本发明提供一种集成半导体存储器件，包括：半导体衬底; 形成在所述半导体衬底中的多个有源区线，每个有源面积线包括具有相应字线接触，位线接触和节点接触的多个存储单元选择晶体管; 布置在所述有源区域线之间的多个填充绝缘沟槽; 多个重新布线条纹，每个重新布线条纹将存储器单元选择晶体管的相关联的节点接触从有源区域线重新连接到相邻的填充绝缘沟槽之上，以形成相应的重新布线的节点接触; 多个位线与所述有源区域线上方对齐并在其上运行，所述有源区线与所述有源区域线的存储单元选择晶体管的位线接点连接; 垂直于所述位线延伸的多个字线，其连接到相应的有源区域线的存储单元选择晶体管的字线触点; 以及多个存储单元电容器，每个存储单元电容器连接到相关联的存储单元选择晶体管的各个重新布线的节点触点。 本发明还提供了一种用于集成半导体存储器件和存储单元的相应制造方法。