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    SEMICONDUCTOR STRUCTURE CONTAINING REENTRANT SHAPED BONDING PADS AND METHODS OF FORMING THE SAME
    43.
    发明申请
    SEMICONDUCTOR STRUCTURE CONTAINING REENTRANT SHAPED BONDING PADS AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210296284A1

    公开(公告)日：2021-09-23

    申请号：US16825304

    申请日：2020-03-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Senaka KANAKAMEDALA ,  Fei ZHOU

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

    MEMORY DEVICE CONTAINING FERROELECTRIC-SPACER-FERROELECTRIC MEMORY ELEMENTS AND METHOD OF MAKING THE SAME
    47.
    发明公开
    MEMORY DEVICE CONTAINING FERROELECTRIC-SPACER-FERROELECTRIC MEMORY ELEMENTS AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20240064995A1

    公开(公告)日：2024-02-22

    申请号：US18161439

    申请日：2023-01-30

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Kartik SONDHI ,  Rahul SHARANGPANI ,  Fei ZHOU

    IPC: H10B51/20 ,  H10B51/30

    CPC classification number: H10B51/20 ,  H10B51/30

    Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and composite layers that are interlaced along a vertical direction, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and an inner ferroelectric material layer including a first ferroelectric material, and a vertical stack of electrically-non-insulating material portions located between the inner ferroelectric material layer and the composite layers. Each of the composite layers includes a respective electrically conductive layer and a respective outer ferroelectric material layer including a second ferroelectric material, embedding the respective electrically conductive layer, and contacting a respective electrically-non-insulating material portion.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING DISCRETE CHARGE STORAGE ELEMENTS AND METHODS OF FORMING THE SAME
    48.
    发明公开
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING DISCRETE CHARGE STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20230171957A1

    公开(公告)日：2023-06-01

    申请号：US18154286

    申请日：2023-01-13

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Fei ZHOU ,  Raghuveer S. MAKALA

    IPC: H10B41/27 ,  G11C16/04 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    CPC classification number: H10B41/27 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method of forming a memory device includes forming an alternating stack of disposable material layers and silicon nitride layers over a substrate, forming a memory opening through the alternating stack, forming a memory film and a vertical semiconductor channel in the memory opening, where the memory film includes a continuous silicon nitride charge storage material layer and a tunneling dielectric layer, forming a backside trench through the alternating stack, forming laterally-extending cavities by removing the disposable material layers selective to the silicon nitride layers through the backside trench, oxidizing portions of the silicon nitride layers and the continuous silicon nitride charge storage material layer exposed in the laterally-extending cavities to form silicon oxide insulating layers and to separate the continuous silicon nitride charge storage material layer into a vertical stack of discrete silicon nitride charge storage material portions, and replacing remaining portions of the silicon nitride layers with electrically conductive layers.

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