公开(公告)号：US11894062B2

公开(公告)日：2024-02-06

申请号：US17398718

申请日：2021-08-10

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink ,  Shubhajit Mukherjee

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/28 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/28 ,  G11C16/34 ,  G11C16/3409 ,  G11C16/3445

Abstract: A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

公开(公告)号：US20230046677A1

公开(公告)日：2023-02-16

申请号：US17398718

申请日：2021-08-10

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink ,  Shubhajit Mukherjee

IPC: G11C16/14 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08 ,  G11C16/34 ,  G11C16/24

Abstract: A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

公开(公告)号：US20230041476A1

公开(公告)日：2023-02-09

申请号：US17392500

申请日：2021-08-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Peter Rabkin ,  Henry Chin ,  Ken Oowada ,  Dengtao Zhao ,  Gerrit Jan Hemink

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

公开(公告)号：US20220406398A1

公开(公告)日：2022-12-22

申请号：US17349321

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G11C29/00 ,  G11C29/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

公开(公告)号：US11328204B2

公开(公告)日：2022-05-10

申请号：US16368347

申请日：2019-03-28

Applicant: SanDisk Technologies LLC

Inventor： Won Ho Choi ,  Pi-Feng Chiu ,  Wen Ma ,  Minghai Qin ,  Gerrit Jan Hemink ,  Martin Lueker-Boden

IPC: G11C16/04 ,  G06N3/04 ,  G11C11/56 ,  G11C13/00 ,  G11C11/16 ,  G06N3/08 ,  G06N3/063 ,  G11C16/26

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.

公开(公告)号：US20210233589A1

公开(公告)日：2021-07-29

申请号：US17227820

申请日：2021-04-12

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US20190115072A1

公开(公告)日：2019-04-18

申请号：US15869592

申请日：2018-01-12

Applicant: SanDisk Technologies LLC

Inventor： Federico Nardi ,  Christopher J. Petti ,  Gerrit Jan Hemink

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/005 ,  G11C2013/0092 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2427 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/249 ,  H01L29/78642 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1683

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.