公开(公告)号：US20200381056A1

公开(公告)日：2020-12-03

申请号：US16994878

申请日：2020-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: G11C16/10 ,  G11C7/10 ,  G11C7/16 ,  G11C11/40

Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.

公开(公告)号：US20200168635A1

公开(公告)日：2020-05-28

申请号：US16657277

申请日：2019-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  H01L29/04 ,  G11C7/04 ,  H03K19/0185 ,  H03K19/00 ,  H01L29/78 ,  H01L49/02 ,  H01L29/786

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20190221586A1

公开(公告)日：2019-07-18

申请号：US16208656

申请日：2018-12-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  H01L29/786 ,  G11C7/04 ,  H03K19/0185 ,  H01L29/04 ,  H01L29/78 ,  H01L49/02 ,  H03K19/00

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20180366185A1

公开(公告)日：2018-12-20

申请号：US16109851

申请日：2018-08-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Hikaru TAMURA

IPC: G11C11/419 ,  H01L29/786 ,  H01L27/105 ,  H01L23/544 ,  G11C11/4076

Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.

公开(公告)号：US20170346489A1

公开(公告)日：2017-11-30

申请号：US15681457

申请日：2017-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: H03K19/00

CPC classification number: H03K19/0013 ,  G09G3/20 ,  G11C7/1006 ,  G11C7/12 ,  G11C11/00 ,  G11C11/401 ,  G11C11/4094 ,  H01L27/10814 ,  H03K19/0966

Abstract: A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor.

公开(公告)号：US20160342000A1

公开(公告)日：2016-11-24

申请号：US15224720

申请日：2016-08-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: G02F1/1333 ,  G06F3/044 ,  G02F1/1339 ,  G06F3/046 ,  G06F3/042 ,  G02F1/1368 ,  G06F3/01 ,  G06F3/045

CPC classification number: G02F1/13338 ,  G02F1/1339 ,  G02F1/1368 ,  G06F3/016 ,  G06F3/041 ,  G06F3/0421 ,  G06F3/044 ,  G06F3/045 ,  G06F3/046 ,  G06F3/0488 ,  G06F3/04886

Abstract: To provide a display device including a touch sensor, in which input feeling can be obtained and deterioration of image quality is suppressed. The display device includes a touch sensor portion, a display panel, an elastic member, and a support. The touch sensor portion is provided over the display panel. The support is provided below the display panel. The elastic member is provided between the display panel and the support. The elastic member is provided in part of the periphery of a pixel region included in the display panel or in the entire periphery.

Abstract translation: 为了提供一种包括触摸传感器的显示装置，其中可以获得输入感觉并且抑制图像质量的劣化。 显示装置包括触摸传感器部分，显示面板，弹性部件和支撑体。 触摸传感器部分设置在显示面板上。 显示面板下面提供支持。 弹性构件设置在显示面板和支撑体之间。 弹性构件设置在包括在显示面板中的像素区域的周边的一部分中或整个周边。

公开(公告)号：US20160233865A1

公开(公告)日：2016-08-11

申请号：US15014081

申请日：2016-02-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA ,  Naoaki TSUTSUI ,  Atsuo ISOBE

IPC: H03K19/00 ,  H01L23/528 ,  H01L27/12 ,  H01L29/786 ,  H01L27/06 ,  H01L27/02 ,  H01L23/532

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1274 ,  H01L29/7869 ,  H03K19/0008

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

Abstract translation: 提供包括堆叠的元件层的半导体器件。 第一布线层和第二布线层堆叠在第一元件层和第二元件层之间。 在第二元件层上堆叠第三布线层和第四布线层。 逻辑单元的晶体管设置在第一元件层中。 逻辑单元的布线设置在第一布线层或第二布线层中。 逻辑单元的输入端口和输出端口设置在第三布线层中。 一个逻辑单元的输入端口通过第三布线层或第四布线层的布线连接到另一逻辑单元的输出端口。 通过第二元件层上的布线层连接逻辑单元提高了布置和连接逻辑单元的步骤的效率。

公开(公告)号：US20150363136A1

公开(公告)日：2015-12-17

申请号：US14731940

申请日：2015-06-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Tomoaki ATSUMI ,  Naoaki TSUTSUI ,  Hikaru TAMURA ,  Takahiko ISHIZU ,  Takuro OHMARU

IPC: G06F3/06 ,  G06F11/14

CPC classification number: G06F12/00 ,  G11C5/00 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7782

Abstract: A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.

Abstract translation: 提供一种包括寄存器控制器和包括寄存器的处理器的半导体器件。 寄存器包括第一电路和包括多个存储器部分的第二电路。 第一电路和多个存储器部分可以通过处理器的算术处理来存储数据。 存储数据的多个存储器部分中的哪一个取决于数据被处理的程序。 寄存器控制器响应中断信号切换程序。 寄存器控制器可以使每次该例程的多个存储器部分中的任何一个存储在第一电路中。 寄存器控制器可以在每次该例程被切换时使存储在与该程序相对应的多个存储器部分中的任何一个存储器中的数据存储在第一电路中。

公开(公告)号：US20150357476A1

公开(公告)日：2015-12-10

申请号：US14827809

申请日：2015-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA ,  Takeshi AOKI

IPC: H01L29/786 ,  H01L31/105 ,  H01L27/146

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/1055 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Abstract translation: 在其中多个像素以矩阵形式布置的CMOS图像传感器中，其中沟道形成区域包括氧化物半导体的晶体管被​​用于处于像素部分的电荷累积控制晶体管和复位晶体管。 在矩阵中排列的所有像素中执行信号电荷累积部分的复位操作之后，在所有像素中执行光电二极管的电荷累积操作，并且每行执行来自像素的信号的读取操作。 因此，可以采取没有失真的图像。

公开(公告)号：US20150279896A1

公开(公告)日：2015-10-01

申请号：US14740720

申请日：2015-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA

IPC: H01L27/146 ,  H01L27/12

CPC classification number: H01L27/14643 ,  G02F1/1362 ,  G02F2001/13312 ,  H01L27/1225 ,  H01L27/14632 ,  H01L27/1464 ,  H04N5/378

Abstract: An object is to achieve low-power consumption by reducing the off-state current of a transistor in a photosensor. A semiconductor device including a photosensor having a photodiode, a first transistor, and a second transistor; and a read control circuit including a read control transistor, in which the photodiode has a function of supplying charge based on incident light to a gate of the first transistor; the first transistor has a function of storing charge supplied to its gate and converting the charge stored into an output signal; the second transistor has a function of controlling reading of the output signal; the read control transistor functions as a resistor converting the output signal into a voltage signal; and semiconductor layers of the first transistor, the second transistor, and the read control transistor are formed using an oxide semiconductor.

Abstract translation: 目的是通过降低光电传感器中的晶体管的截止电流来实现低功耗。 一种半导体器件，包括具有光电二极管的光传感器，第一晶体管和第二晶体管; 以及包括读取控制晶体管的读取控制电路，其中光电二极管具有基于入射光向第一晶体管的栅极提供电荷的功能; 第一晶体管具有存储提供给其栅极的电荷并将存储的电荷转换为输出信号的功能; 第二晶体管具有控制输出信号的读取的功能; 读控制晶体管用作将输出信号转换成电压信号的电阻器; 并且使用氧化物半导体形成第一晶体管，第二晶体管和读控制晶体管的半导体层。