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    SEMICONDUCTOR DEVICE
    42.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240396105A1

    公开(公告)日：2024-11-28

    申请号：US18676728

    申请日：2024-05-29

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Ryota TAJIMA ,  Kei TAKAHASHI ,  Hiroki INOUE ,  Munehiro KOZUMA ,  Takahiro FUKUTOME

    IPC: H01M10/44 ,  G01R31/367 ,  H01M10/48 ,  H02J7/00

    Abstract: A semiconductor device that inhibits deterioration of a secondary battery is provided. The semiconductor device includes a secondary battery module and a first circuit. The secondary battery module includes a secondary battery and a sensor. The first circuit includes a variable resistor. The sensor has a function of measuring a temperature of the secondary battery. The first circuit has a function of judging the charge voltage of the secondary battery and outputting a first result; a function of judging the temperature of the secondary battery measured by the sensor and outputting a second result; a function of determining the magnitude of the variable resistor on the basis of the first result and the second result; a function of discharging the charge voltage through the variable resistor; and a function of stopping discharge when the charge voltage reaches a specified voltage.

    LOGIC CIRCUIT FORMED USING UNIPOLAR TRANSISTOR, AND SEMICONDUCTOR DEVICE
    43.
    发明公开
    LOGIC CIRCUIT FORMED USING UNIPOLAR TRANSISTOR, AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240364343A1

    公开(公告)日：2024-10-31

    申请号：US18766726

    申请日：2024-07-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Shuji FUKAI ,  Fumika AKASAWA ,  Shintaro HARADA ,  Sho NAGAO

    IPC: H03K19/094 ,  H01L27/06

    CPC classification number: H03K19/094 ,  H01L27/0629

    Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

    MEMORY DEVICE
    44.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20240147687A1

    公开(公告)日：2024-05-02

    申请号：US18382075

    申请日：2023-10-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takanori MATSUZAKI ,  Hiroki INOUE ,  Yuki OKAMOTO

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A memory device that can be highly integrated is provided. The memory device includes a first transistor and a second transistor in a memory cell, and small-area vertical transistors each including a channel formation region on a side surface of an opening portion provided in an insulating layer are used as the two transistors. The memory cell includes a conductor having a function of a gate electrode of the first transistor and a function of one of a source electrode and a drain electrode of the second transistor. The memory cells are placed in a staggered arrangement, so that the memory device can be highly integrated.

    IMAGING DEVICE, OPERATION METHOD THEREOF, AND ELECTRONIC DEVICE
    46.
    发明公开
    IMAGING DEVICE, OPERATION METHOD THEREOF, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230247331A1

    公开(公告)日：2023-08-03

    申请号：US17768972

    申请日：2020-10-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Seiichi YONEDA ,  Hiroki INOUE

    IPC: H04N25/78 ,  H04N25/709 ,  H04N25/77

    CPC classification number: H04N25/78 ,  H04N25/709 ,  H04N25/77 ,  H10K39/32

    Abstract: An imaging device with low power consumption is provided. A pixel includes a first circuit and a second circuit. The first circuit can generate imaging data and retain difference data that is a difference between the imaging data and data obtained in an initial frame. The second circuit includes a circuit that compares the difference data and a voltage range set arbitrarily. The second circuit supplies a reading signal based on the comparison result. With the use of the structure, reading from the pixel is not performed when it is determined that the difference data is within the set voltage range and reading from the pixel can be performed when it is determined that the difference data is outside the voltage range.

    SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING SEMICONDUCTOR DEVICE
    48.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220321006A1

    公开(公告)日：2022-10-06

    申请号：US17621338

    申请日：2020-06-24

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Kousuke SASAKI ,  Yuto YAKUBO ,  Kei TAKAHASHI

    IPC: H02M3/156 ,  H02H7/18 ,  H01L27/12 ,  H01L29/786

    Abstract: A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.

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