公开(公告)号：US10483393B2

公开(公告)日：2019-11-19

申请号：US15798976

申请日：2017-10-31

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US10199392B2

公开(公告)日：2019-02-05

申请号：US15169462

申请日：2016-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Ronald K. Sampson ,  Nicolas Loubet

IPC: H01L27/14 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L29/06 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L21/265 ,  H01L21/308 ,  H01L29/167 ,  H01L29/49

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

公开(公告)号：US10170546B2

公开(公告)日：2019-01-01

申请号：US15873644

申请日：2018-01-17

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L31/072 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/16 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

公开(公告)号：US10074577B2

公开(公告)日：2018-09-11

申请号：US15220150

申请日：2016-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161

CPC classification number: H01L21/845 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161

Abstract: A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.

公开(公告)号：US09793378B2

公开(公告)日：2017-10-17

申请号：US13906677

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7848 ,  H01L29/785

Abstract: Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.

公开(公告)号：US09640641B2

公开(公告)日：2017-05-02

申请号：US14800381

申请日：2015-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  Nicolas Loubet ,  Junli Wang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/225 ,  H01L29/78 ,  H01L29/167

CPC classification number: H01L29/785 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2256 ,  H01L21/31116 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

公开(公告)号：US09620506B2

公开(公告)日：2017-04-11

申请号：US13907411

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare ,  Stephane Allegret-Maret ,  Bruce Doris ,  Kangguo Cheng

IPC: H01L27/088 ,  H01L27/092 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

公开(公告)号：US20170047406A1

公开(公告)日：2017-02-16

申请号：US15340624

申请日：2016-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  Nicolas Loubet ,  Junli Wang

IPC: H01L29/10 ,  H01L29/161 ,  H01L21/225 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2256 ,  H01L21/31116 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

公开(公告)号：US09530777B2

公开(公告)日：2016-12-27

申请号：US14196596

申请日：2014-03-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Hong He ,  James Kuss

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Methods and structures for forming finFETs of different semiconductor composition and of different conductivity type on a same wafer are described. Some finFET structures may include strained channel regions. FinFETs of a first semiconductor composition may be grown in trenches formed in a second semiconductor composition. Material of the second semiconductor composition may be removed from around some of the fins at first regions of the wafer, and may remain around fins at second regions of the wafer. A chemical component from the second semiconductor composition may be driven into the fins by diffusion at the second regions to form finFETs of a different chemical composition from those of the first regions. The converted fins at the second regions may include strain.

Abstract translation: 描述了在同一晶片上形成不同半导体组成和不同导电类型的finFET的方法和结构。 一些finFET结构可以包括应变通道区域。 可以在第二半导体组合物中形成的沟槽中生长第一半导体组合物的FinFET。 第二半导体组合物的材料可以从晶片的第一区域周围的一些鳍片周围去除，并且可以保留在晶片的第二区域周围的鳍片周围。 来自第二半导体组合物的化学成分可以通过在第二区域的扩散而被驱入散热片，以形成与第一区域不同的化学组成的finFET。 在第二区域处的转换的翅片可以包括应变。

公开(公告)号：US09466720B2

公开(公告)日：2016-10-11

申请号：US14675156

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L29/49 ,  H01L29/165 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L21/225 ,  H01L27/092

CPC classification number: H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.