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    SEMICONDUCTOR DEVICES HAVING EXPANDED RECESS FOR BIT LINE CONTACT
    42.
    发明申请
    SEMICONDUCTOR DEVICES HAVING EXPANDED RECESS FOR BIT LINE CONTACT 有权
    具有扩展接口的半导体器件

    公开(公告)号：US20160181198A1

    公开(公告)日：2016-06-23

    申请号：US14971402

    申请日：2015-12-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DAEIK KIM ,  Jemin Park ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L23/522 ,  H01L29/06 ,  H01L27/108

    CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10897 ,  H01L29/4236 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.

    Abstract translation: 半导体器件包括第一器件隔离区和限定衬底中的第一有源区，第二有源区和第三有源区的第二器件隔离区，暴露第一有源区的上表面的凹陷区和上表面 的第一和第二器件隔离区域以及第二和第三有效区域上的主动缓冲器图案。 第一有源区位于第二和第三有源区之间，第一器件隔离区位于第一和第二有源区之间，第二器件隔离区位于第一和第三有源区之间。 第二和第三有源区域的上侧壁在凹陷区域中露出。

    Method of fabricating semiconductor memory device having protruding contact portion
    43.
    发明授权
    Method of fabricating semiconductor memory device having protruding contact portion 有权

    公开(公告)号：US12279415B2

    公开(公告)日：2025-04-15

    申请号：US18337134

    申请日：2023-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

    IPC: H10B12/00 ,  G11C5/12

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    Semiconductor device including storage node electrode including step and method of manufacturing the semiconductor device
    46.
    发明授权
    Semiconductor device including storage node electrode including step and method of manufacturing the semiconductor device 有权

    公开(公告)号：US11610891B2

    公开(公告)日：2023-03-21

    申请号：US17725806

    申请日：2022-04-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehwan Cho ,  Junghwan Oh ,  Sangho Lee ,  Junwon Lee ,  Jinwoo Bae ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

    SEMICONDUCTOR MEMORY DEVICES
    47.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220278121A1

    公开(公告)日：2022-09-01

    申请号：US17748261

    申请日：2022-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

    IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524

    Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

    Semiconductor devices including support pattern and methods of fabricating the same
    48.
    发明授权
    Semiconductor devices including support pattern and methods of fabricating the same 有权

    公开(公告)号：US11348996B2

    公开(公告)日：2022-05-31

    申请号：US16860136

    申请日：2020-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwan Cho ,  Sangho Lee ,  Yoosang Hwang

    IPC: H01L49/02 ,  H01L27/108 ,  H01L27/02

    Abstract: Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.

    SEMICONDUCTOR DEVICES INCLUDING SUPPORT PATTERN AND METHODS OF FABRICATING THE SAME
    49.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING SUPPORT PATTERN AND METHODS OF FABRICATING THE SAME 有权

    公开(公告)号：US20220130950A1

    公开(公告)日：2022-04-28

    申请号：US17568780

    申请日：2022-01-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwan Cho ,  Sangho Lee ,  Yoosang Hwang

    IPC: H01L49/02 ,  H01L27/108 ,  H01L27/02

    Abstract: Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.

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