公开(公告)号：US12191368B2

公开(公告)日：2025-01-07

申请号：US17455681

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghee Park ,  Munhyeon Kim ,  Uihui Kwon ,  Joohyung You ,  Daewon Ha

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

Abstract: A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

公开(公告)号：US12159939B2

公开(公告)日：2024-12-03

申请号：US17724619

申请日：2022-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Doyoung Choi ,  Daewon Ha ,  Mingyu Kim

IPC: H01L29/786

Abstract: A semiconductor device includes an active pattern on a substrate, a plurality of source/drain patterns in a first direction on the active pattern, a first channel structure between a pair of source/drain patterns, a second channel structure between another pair of source/drain patterns, a first gate electrode extending in a second direction perpendicular to the first direction, and a second gate electrode intersecting the second channel structure and extending in the second direction. The first gate electrode includes a first portion between a bottom surface of the first channel structure and a top surface of the active pattern, and the second gate electrode includes a first portion between a bottom surface of the second channel structure and the top surface of the active pattern. A thickness of the first portion of the second gate electrode is greater than a thickness of the first portion of the first gate electrode.

公开(公告)号：US20240397726A1

公开(公告)日：2024-11-28

申请号：US18655488

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilho Myeong ,  Yongseok Kim ,  Taeyoung Kim ,  Suseong Noh ,  Sanghyun Park ,  Suhwan Lim ,  Daewon Ha

IPC: H10B51/20 ,  H01L25/065 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B80/00

Abstract: A semiconductor device includes a stacked structure including a plurality of gate lines and a plurality of insulation patterns that are alternately stacked in a vertical direction, where the stacked structure defines a vertical hole that extends into the stacked structure and in the vertical direction, a channel film that extends into a vertical hole, and a multiple dielectric layer structure between the channel film and the stacked structure, where the multiple dielectric layer structure includes a plurality of interlayer dielectric layers and a plurality of ferroelectric layers that are alternately stacked and extend from the channel film toward the stacked structure, and where an inner ferroelectric layer of the plurality of ferroelectric layers is thicker than an outer ferroelectric layer of the plurality of ferroelectric layers.

公开(公告)号：US20240324239A1

公开(公告)日：2024-09-26

申请号：US18612011

申请日：2024-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daewon Ha ,  Kyunghwan Lee ,  Myunghun Woo

IPC: H10B53/30 ,  G11C5/06 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

CPC classification number: H10B53/30 ,  G11C5/063 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

Abstract: A semiconductor memory device includes a plurality of memory cells each including a first vertical channel transistor (VCT) and a second VCT arranged in a vertical direction and connected to each other in series, the plurality of memory cells respectively including a plurality of ferroelectric capacitors connected to the second VCT in parallel and arranged in the vertical direction, wherein the plurality of memory cells are arranged in columns and rows in a first horizontal direction and a second horizontal direction that is different from the first horizontal direction.

公开(公告)号：US20240178229A1

公开(公告)日：2024-05-30

申请号：US18430902

申请日：2024-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Mingyu Kim ,  Doyoung Choi ,  Daewon Ha

IPC: H01L27/092

CPC classification number: H01L27/0922

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.

公开(公告)号：US11908861B2

公开(公告)日：2024-02-20

申请号：US17394580

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Mingyu Kim ,  Doyoung Choi ,  Daewon Ha

IPC: H01L27/092

CPC classification number: H01L27/0922

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.

公开(公告)号：US20240015975A1

公开(公告)日：2024-01-11

申请号：US18108722

申请日：2023-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suseong Noh ,  Yongseok Kim ,  Daewon Ha

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: A semiconductor device may include first conductive lines on a substrate and spaced apart from each other in a first direction, second conductive lines spaced apart from the first conductive lines in a second direction, third conductive lines spaced apart from the second conductive lines in the second direction, gate electrodes between the first, second and third conductive lines and extending in the first direction, ferroelectric patterns on respective side surfaces of the gate electrodes, gate insulating patterns on the respective side surfaces of the gate electrodes and spaced apart from the respective side surfaces of the gate electrodes with the ferroelectric patterns respectively therebetween, and channel patterns extending along respective side surfaces of the gate insulating patterns. Each of the channel patterns may be electrically connected to the second conductive lines, respectively, and may be electrically connected to the first conductive lines or the third conductive lines, respectively.

公开(公告)号：US20230170398A1

公开(公告)日：2023-06-01

申请号：US17834527

申请日：2022-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil Park ,  Jae Hyun Park ,  Daewon Ha

IPC: H01L29/49 ,  H01L29/12 ,  H01L29/423

CPC classification number: H01L29/4925 ,  H01L29/12 ,  H01L29/42312

Abstract: Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

公开(公告)号：US11588054B2

公开(公告)日：2023-02-21

申请号：US17240616

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20230049858A1

公开(公告)日：2023-02-16

申请号：US17720741

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Keun Hwi Cho ,  Daewon Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.