公开(公告)号：US12230570B2

公开(公告)日：2025-02-18

申请号：US17574073

申请日：2022-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Kang-ill Seo ,  Mark S. Rodder

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L29/06

Abstract: A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.

公开(公告)号：US20240379653A1

公开(公告)日：2024-11-14

申请号：US18782939

申请日：2024-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Traynor ,  Tanya Abaya ,  Dharmendar Palle ,  Mark S. Rodder

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/528

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

公开(公告)号：US10957786B2

公开(公告)日：2021-03-23

申请号：US16282105

申请日：2019-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Borna J. Obradovic ,  Mark Stephen Rodder

IPC: H01L21/70 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/223 ,  H01L21/225 ,  H01L29/78 ,  H01L29/10 ,  H01L29/167

Abstract: A method of manufacturing a field effect transistor includes forming a fin on a substrate, forming source and drain electrodes on opposite sides of the fin, forming a gate stack on a channel portion of the fin between the source and drain electrodes, forming gate spacers on extension portions of the fin on opposite sides of the gate stack, removing at least portions of the gate spacers to expose the extension portions of the fin, and hydrogen annealing the extension portions of the fin. Following the hydrogen annealing of the extension portions of the fin, the channel portion of the fin has a first width and the extension portions of the fin have a second width greater than the first width.

公开(公告)号：US10381315B2

公开(公告)日：2019-08-13

申请号：US15927239

申请日：2018-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L31/062 ,  H01L23/00 ,  H01L23/522 ,  H01L27/02 ,  H04L9/32 ,  H01L23/532

Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

公开(公告)号：US20190148502A1

公开(公告)日：2019-05-16

申请号：US16121427

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02

Abstract: A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US20190148298A1

公开(公告)日：2019-05-16

申请号：US15948543

申请日：2018-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L23/535 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US10181527B2

公开(公告)日：2019-01-15

申请号：US15169621

申请日：2016-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dharmendar Reddy Palle ,  Borna Obradovic ,  Joon Goo Hong ,  Mark Rodder

IPC: H01L29/78 ,  H01L29/66

Abstract: A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.

公开(公告)号：US10164121B2

公开(公告)日：2018-12-25

申请号：US15181327

申请日：2016-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic ,  Joon Goo Hong ,  Rwik Sengupta

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.

公开(公告)号：US09905672B2

公开(公告)日：2018-02-27

申请号：US15276784

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Reddy Palle ,  Joon Goo Hong

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/04

CPC classification number: H01L29/66553 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0259 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78

Abstract: A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

公开(公告)号：US20180053690A1

公开(公告)日：2018-02-22

申请号：US15343157

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/82345 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28185 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (hNS devices) on a top surface of a substrate, the plurality of hNS devices including a first hNS device and a second hNS device spaced apart from each other horizontally. Each of the hNS devices includes a first and a second horizontal nanosheets spaced apart vertically; and a gate stack between the first and second horizontal nanosheets, the gate stack including a work function metal (WFM) layer. A thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.