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公开(公告)号：US20240107767A1
公开(公告)日：2024-03-28
申请号：US18463620
申请日：2023-09-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhyoung Kim , Joonyoung Kwon , Jiyoung Kim , Jinhyuk Kim , Sukkang Sung
IPC: H10B43/27
CPC classification number: H10B43/27
Abstract: A semiconductor device includes a gate electrode structure, a first division pattern, and a memory channel structure. The gate electrode structure includes gate electrodes stacked in a first direction and extending in a second direction. The first division pattern extends in the second direction through the gate electrode structure, and divides the gate electrode structure in a third direction. The memory channel structure extends through the gate electrode structure, and includes a channel and a charge storage structure. The first division pattern includes first and second sidewalls opposite to each other in the third direction. First recesses are spaced apart from each other in the second direction on the first sidewall, and second recesses are spaced apart from each other in the second direction on the second sidewall. The first and second recesses do not overlap in the third direction.
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公开(公告)号：US20240099012A1
公开(公告)日：2024-03-21
申请号：US18308222
申请日：2023-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joonyoung Kwon , Jiyoung Kim , Junhyoung Kim , Sukkang Sung
Abstract: A semiconductor device includes a peripheral circuit structure including a plurality of circuit areas, a cell array structure including a pair of memory cell blocks overlapping the peripheral circuit structure in a first direction and spaced apart in a second direction, perpendicular to the first direction, with a peripheral circuit connection area therebetween, a first circuit area of the plurality of circuit areas that overlaps the peripheral circuit connection area in the first direction, and at least one contact plug extending in the first direction from the peripheral circuit connection area, and including a first end portion configured to connect to at least one circuit included in the first circuit area and facing the first circuit area and a second end portion configured to connect to an external connection terminal.
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公开(公告)号：US11839091B2
公开(公告)日：2023-12-05
申请号：US17011156
申请日：2020-09-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhyoung Kim , Kwang-Soo Kim , Bonghyun Choi , Siwan Kim
Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.
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公开(公告)号：US11737270B2
公开(公告)日：2023-08-22
申请号：US17897255
申请日：2022-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhyoung Kim , Jisung Cheon , Yoonhwan Son , Seungmin Lee
Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.
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Patent Agency Ranking
公开(公告)号：US20230080606A1
公开(公告)日：2023-03-16
申请号：US17852812
申请日：2022-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungmin Lee , Junhyoung Kim , Kangmin Kim , Joonsung Lim
IPC: H01L27/11573 , H01L27/11519 , H01L23/528 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
Abstract: A semiconductor device may include: a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a plate pattern on the peripheral circuit structure and having a gap; and a stack structure on the plate pattern and including a first stack region and a second stack region. The first stack region may include gate electrodes stacked in a vertical direction perpendicular to an upper surface of the semiconductor substrate, and the second stack region may include both a conductor stack region including conductive layers stacked in the vertical direction and an insulator stack region including molded insulating layers at substantially the same height level as the conductive layers. The semiconductor device may also include vertical memory structure that extends through the first stack region; and source contact plugs electrically connected to at least one of the conductive layers of the conductor stack region and contacting the plate pattern.
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公开(公告)号：US20220375862A1
公开(公告)日：2022-11-24
申请号：US17563275
申请日：2021-12-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhyoung Kim , Kangmin Kim , Taemin Eom , Seungmin Lee , Changsun Hwang
IPC: H01L23/535 , H01L27/11556 , H01L27/11582
Abstract: A semiconductor device includes a substrate including a cell array region and a contact region; a plurality of gate electrodes arranged on the substrate in a first direction perpendicular to an upper surface of the substrate, the plurality of gate electrodes being extending in the cell array region and the contact region; a plurality of channel structures penetrating the plurality of gate electrodes in the first direction in the cell array region; a plurality of dummy channel structures penetrating the plurality of gate electrodes in the first direction in the contact region; a plurality of cell gate contacts extending in the first direction and each electrically connected to a respective one of the plurality of gate electrodes in the contact region; and a plurality of dummy contacts extending in the first direction on the plurality of dummy channel structures.
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公开(公告)号：US20220367359A1
公开(公告)日：2022-11-17
申请号：US17567249
申请日：2022-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhyoung Kim , Kangmin Kim , Changhwan Lee , Taemin Eom , Seungmin Lee
IPC: H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573
Abstract: A semiconductor device includes a first structure including a substrate, circuit devices, a lower interconnection structure electrically connected to the circuit devices, and a second structure on the first structure. The second structure includes a conductive plate layer; gate electrodes on the conductive plate layer and extending in a first direction; separation regions penetrating through the gate electrodes and extending in the first direction; channel structures penetrating through the gate electrodes and respectively including a channel layer; through-contact plugs spaced apart from the gate electrodes and extending in the vertical direction to be electrically connected to the lower interconnection structure of the first structure; first and second contacts electrically connected to the channel layer and the through-contact plugs, respectively; bitlines electrically connecting at least one of each of the first and second contacts to each other; and dummy contacts connected to the bitlines and spaced apart from the through-contact plugs.
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公开(公告)号：US20210036001A1
公开(公告)日：2021-02-04
申请号：US16842907
申请日：2020-04-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhyoung Kim , Taemok Gwon , Youngbum Woo
IPC: H01L27/11556 , H01L27/11582 , H01L27/07 , H01L23/522
Abstract: A vertical memory device includes lower circuit patterns, a second substrate, a capacitor, gate electrodes, and a channel. The lower circuit patterns are formed on a first substrate including first, second and third regions. Contact plugs are formed in the second region. Through vias are formed in the third region. The second substrate is formed on the lower circuit patterns. The capacitor is formed on the lower circuit patterns, and includes a first conductor, a dielectric layer structure, and a second conductor. The first conductor is spaced apart from the second substrate at the same height as the second substrate. The dielectric layer structure is formed on the first conductor. The second conductor is formed on the dielectric layer structure. The gate electrodes are spaced apart from each other on the second substrate in a vertical direction. The channel extends through the gate electrodes in the vertical direction.
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公开(公告)号：US20210020656A1
公开(公告)日：2021-01-21
申请号：US16802736
申请日：2020-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhyoung Kim , Geunwon Lim , Manjoong Kim
IPC: H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11556
Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.
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