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    METHODS OF OPERATING MEMORY CONTROLLERS, MEMORY CONTROLLERS PERFORMING THE METHODS AND MEMORY SYSTEMS INCLUDING THE MEMORY CONTROLLERS
    41.
    发明申请
    METHODS OF OPERATING MEMORY CONTROLLERS, MEMORY CONTROLLERS PERFORMING THE METHODS AND MEMORY SYSTEMS INCLUDING THE MEMORY CONTROLLERS 有权

    公开(公告)号：US20230004308A1

    公开(公告)日：2023-01-05

    申请号：US17704354

    申请日：2022-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee

    IPC: G06F3/06

    Abstract: In a method of operating a memory controller, a decoding status flag is received from a memory module including a plurality of data chips and at least one parity chip. Each of the plurality of data chips and the at least one parity chip may include an on-die error correction code (ECC) engine. The decoding status flag is generated by the on-die ECC engines. A first number and a second number may be obtained based on the decoding status flag. The first number represents a number of first chips including an uncorrectable error that is uncorrectable by the on-die ECC engine. The second number represents a number of second chips including a correctable error that is correctable by the on-die ECC engine. At least one of a plurality of decoding schemes is selected based on at least one of the first number and the second number. A system ECC engine may perform ECC decoding on at least one of the first chips and the second chips based on the selected decoding scheme.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    42.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20220270661A1

    公开(公告)日：2022-08-25

    申请号：US17408454

    申请日：2021-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunghye Cho ,  Kijun Lee ,  Eunae Lee

    IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4091

    Abstract: A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when t the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    43.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11314592B2

    公开(公告)日：2022-04-26

    申请号：US16909730

    申请日：2020-06-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee

    IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4091 ,  G11C11/56 ,  G11C11/4093 ,  H01L25/065

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t−2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.

    ERROR CORRECTION DEVICE AND METHOD FOR GENERATING SYNDROMES AND PARTIAL COEFFICIENT INFORMATION IN A PARALLEL
    44.
    发明申请
    ERROR CORRECTION DEVICE AND METHOD FOR GENERATING SYNDROMES AND PARTIAL COEFFICIENT INFORMATION IN A PARALLEL 有权

    公开(公告)号：US20210384919A1

    公开(公告)日：2021-12-09

    申请号：US17199803

    申请日：2021-03-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunae Lee ,  Kijun Lee ,  Yeonggeol Song ,  Myungkyu Lee ,  Seokha Hwang

    IPC: H03M13/15 ,  G06F11/10

    Abstract: An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME
    45.
    发明申请
    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20210194508A1

    公开(公告)日：2021-06-24

    申请号：US16987554

    申请日：2020-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Chanki Kim ,  Yeonggeol Song

    IPC: H03M13/15 ,  H03M13/11 ,  G06F11/10 ,  G06F9/30

    Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS WITH ENHANCED ERROR DETECTION AND CORRECTION
    46.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS WITH ENHANCED ERROR DETECTION AND CORRECTION 有权

    公开(公告)号：US20210191810A1

    公开(公告)日：2021-06-24

    申请号：US16934677

    申请日：2020-07-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunghye Cho ,  Chanki Kim ,  Kijun Lee ,  Sanguhn Cha ,  Myungkyu Lee

    IPC: G06F11/10 ,  H03M13/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array is coupled to word-line and bit-lines and is divided into sub array blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I/O gating circuit based on a command and address. The control logic circuit stores the main data and the parity data in (k+1) target sub array blocks in the second direction among the sub array blocks, and controls the I/O gating circuit such that a portion of the (k+1) target sub array blocks store both of a portion of the main data and a portion of the parity data.

    Memory device and refresh method thereof
    48.
    发明授权
    Memory device and refresh method thereof 有权

    公开(公告)号：US12236996B2

    公开(公告)日：2025-02-25

    申请号：US18197084

    申请日：2023-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eun Ae Lee ,  Sunghye Cho ,  Kijun Lee ,  Kyomin Sohn ,  Myungkyu Lee

    IPC: G11C11/406

    Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

    Semiconductor memory devices
    49.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US12066893B2

    公开(公告)日：2024-08-20

    申请号：US18226622

    申请日：2023-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

    IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28

    CPC classification number: G06F11/1068

    Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME
    50.
    发明公开
    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240178861A1

    公开(公告)日：2024-05-30

    申请号：US18339490

    申请日：2023-06-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiho Kim ,  Seongmuk Kang ,  Daehyun Kim ,  Kijun Lee ,  Myungkyu Lee ,  Kyomin Sohn ,  Sunghye Cho

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/1111 ,  H03M13/611

    Abstract: A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.

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