公开(公告)号：US20210125980A1

公开(公告)日：2021-04-29

申请号：US17132699

申请日：2020-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Dongoh KIM ,  Myeong-Dong LEE

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

公开(公告)号：US20190326278A1

公开(公告)日：2019-10-24

申请号：US16288590

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Dongoh KIM ,  Myeong-Dong LEE

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

公开(公告)号：US20180158871A1

公开(公告)日：2018-06-07

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/24 ,  H01L27/22 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/228 ,  H01L27/2436

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20160110056A1

公开(公告)日：2016-04-21

申请号：US14883940

申请日：2015-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohy HONG ,  Kyungwhoon CHEUN ,  Jisung OH ,  Kiseok LEE ,  Dongjoo CHOI

IPC: G06F3/0481 ,  G06F3/0484 ,  G06F3/0488

CPC classification number: G06F3/04812 ,  G06F3/04842 ,  G06F3/04883

Abstract: The present disclosure relates to a sensor network, Machine Type Communication (MTC), Machine-to-Machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method of providing a user interface (UI) by an electronic device is provided. The method includes displaying a control UI, receiving a first drag input via the displayed control UI, and, when a direction of the first drag input corresponds to a first direction, displaying a cursor UI at a preset location. According to an embodiment of the present disclosure, a UI through which an electronic device can easily receive a user input may be provided.

Abstract translation: 本公开涉及传感器网络，机器类型通信（MTC），机器对机器（M2M）通信和物联网技术（IoT）。 本发明可以应用于智能家居，智能建筑，智能城市，智能汽车，连接车，医疗保健，数字教育，智能零售，安全和安全服务等上述技术的智能化服务。 提供了一种通过电子设备提供用户界面（UI）的方法。 该方法包括显示控制UI，经由显示的控制UI接收第一拖动输入，并且当第一拖动输入的方向对应于第一方向时，在预设位置显示光标UI。 根据本公开的实施例，可以提供电子设备可以容易地接收用户输入的UI。

公开(公告)号：US20250040129A1

公开(公告)日：2025-01-30

申请号：US18655731

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungbo KO ,  Inwoo KIM ,  Jongmin KIM ,  Kiseok LEE ,  Minyoung LEE ,  Seongtak CHO ,  Inho CHA

IPC: H10B12/00

Abstract: A semiconductor device may include a device isolation layer on a side of the active region, a gate trench intersecting the active region, a gate structure in the gate trench, a bit line electrically connected to a first region of the active region, and a pad pattern electrically connected to a second region of the active region. An upper surface of the second region may be higher than an upper surface of the first region and lower than an upper surface of the bit line. A width of the bit line may be greater in an upper region than a lower region thereof. The pad pattern may contact upper and side surfaces of the second region. An upper surface of the pad pattern may be higher than an upper surface of the bit line. The gate trench may be between the first and second regions of the active region.

公开(公告)号：US20240341081A1

公开(公告)日：2024-10-10

申请号：US18388295

申请日：2023-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun LEE ,  Keunnam KIM ,  Seungmuk KIM ,  Kiseok LEE

IPC: H10B12/00 ,  G11C5/06

CPC classification number: H10B12/315 ,  G11C5/063 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device which includes a semiconductor substrate having a cell area and a peripheral area, the peripheral area including a first area and a second area adjacent to each other, first transistors on the first area, a first wiring layer on the first transistors, a first pad on the second area and a portion of the first area, a first contact plug between the first wiring layer and the first area, a second contact plug between the first pad and the first area, a second pad on the first wiring layer, a third contact plug between the second pad and the first wiring layer, and a plurality of first capacitors on the second pad and that vertically overlap the first transistors, thus reliability and electrical characteristics of the semiconductor device may be increased.

公开(公告)号：US20240284657A1

公开(公告)日：2024-08-22

申请号：US18529698

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho CHOI ,  Kiseok LEE ,  Chansic YOON ,  Chulkwon PARK ,  Jaybok CHOI

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a substrate having a plurality of active regions and defining a plurality of first gate trenches and a plurality of second gate trenches crossing the plurality of active regions and extending in a first horizontal direction, a plurality of gate structures including a plurality of first gate structures within the plurality of first gate trenches and a plurality of second gate structures within the plurality of second gate trenches, a bit line structure crossing the plurality of gate structures and extending in a second horizontal direction that intersects the first horizontal direction, and a contact plug disposed on a side surface of the bit line structure. When viewed in plan view, an area of at least some of the plurality of first gate structures is different from an area of at least some of the plurality of second gate structures.

公开(公告)号：US20240268123A1

公开(公告)日：2024-08-08

申请号：US18370207

申请日：2023-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Jinwoo HAN ,  Hanjin LIM

IPC: H10B53/30 ,  H10B53/40

CPC classification number: H10B53/30 ,  H10B53/40

Abstract: A semiconductor device includes gate structure, bit line structure, contact plug structure, stack structure, and capacitor. The gate structure is disposed on first substrate. The bit line structure is disposed on the gate structure. The contact plug structure is disposed on the first substrate and spaced apart from the bit line structure. The stack structure is disposed on the bit line structure and the contact plug structure, and may include insulation layers and plate electrodes alternately stacked in a vertical direction substantially perpendicular to an upper surface of the first substrate. The capacitor includes a second electrode extending through the stack structure and contacting the contact plug structure. A ferroelectric pattern is disposed on a sidewall of the second electrode. First electrodes are disposed on a sidewall of the ferroelectric pattern, contact sidewalls of the plate electrodes, respectively, and are spaced apart from each other in the vertical direction.

公开(公告)号：US20240268101A1

公开(公告)日：2024-08-08

申请号：US18471900

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SangJae PARK ,  Seung-Bo KO ,  Keunnam KIM ,  Jongmin KIM ,  Hui-Jung KIM ,  Taejin PARK ,  Chan-Sic YOON ,  Kiseok LEE ,  Myeong-Dong LEE ,  Hongjun LEE

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/34 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes first and second active patterns extending in a first direction and being adjacent to each other in a second direction, the first and second active patterns, each of which includes first and second edges spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge of the first active pattern, a second storage node pad and a second storage node contact sequentially provided on the second edge of the second active pattern, and a fence pattern between the first and the second storage node contacts. Bottom and top surfaces of the first storage node contact are located at first and second levels, respectively. In a third direction, a width of the fence pattern at the first level is less than a width of the fence pattern at the second level.

公开(公告)号：US20240006250A1

公开(公告)日：2024-01-04

申请号：US18150324

申请日：2023-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunnam KIM ,  Kiseok LEE ,  Byeongjoo KU

IPC: H01L21/66 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L22/20 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76879 ,  H01L21/76816

Abstract: Disclosed is a semiconductor fabrication method comprising forming a first conductive structure and a second conductive structure, measuring a misalignment value between the first conductive structure and the second conductive structure, based on the measured misalignment value selecting a reticle from a set of reticles, and using the selected reticle to form a connection conductive structure that electrically connects the first conductive structure to the second conductive structure.