公开(公告)号：US20240179946A1

公开(公告)日：2024-05-30

申请号：US18274036

申请日：2022-01-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Tatsuya ONUKI

IPC: H10K59/121 ,  H10K50/19

CPC classification number: H10K59/1213 ,  H10K50/19

Abstract: A novel semiconductor device is provided. The semiconductor device includes a first layer; a second layer over the first layer; and a third layer over the second layer. The first layer includes a functional circuit including a first transistor, the second layer includes a plurality of pixel circuits each including a second transistor, the third layer includes a plurality of light-emitting elements, one of the plurality of pixel circuits is electrically connected to one of the plurality of light-emitting elements, the functional circuit has a function of controlling an operation of the pixel circuit, and the pixel circuit has a function of controlling emission luminance of the light-emitting element.

公开(公告)号：US20240090284A1

公开(公告)日：2024-03-14

申请号：US18273095

申请日：2022-01-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Tatsuya ONUKI ,  Takayuki IKEDA ,  Takanori MATSUZAKI

IPC: H10K59/131 ,  G09G3/3258 ,  H10K59/121

CPC classification number: H10K59/131 ,  G09G3/3258 ,  H10K59/1213 ,  G09G2300/0426 ,  G09G2310/0297

Abstract: A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings. The plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions.

公开(公告)号：US20240057404A1

公开(公告)日：2024-02-15

申请号：US18271541

申请日：2022-01-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Kenichi OKAZAKI ,  Yasumasa YAMANE

IPC: H10K59/124 ,  H10K59/35 ,  H10K50/19 ,  H10K50/13

CPC classification number: H10K59/124 ,  H10K59/353 ,  H10K50/19 ,  H10K50/13

Abstract: A high-resolution display device is provided. A display device with both high display quality and high resolution is provided. The display device includes a first light-emitting element and a second light-emitting element. The first light-emitting element includes a first pixel electrode, a first EL layer, and a common electrode. The second light-emitting element includes a second pixel electrode, a second EL layer, and the common electrode. An insulating layer is included between the first pixel electrode and the second pixel electrode. The insulating layer includes a first region overlapping with the first EL layer, a second region overlapping with the second EL layer, and a third region positioned between the first region and the second region. A side surface of the first EL layer and a side surface of the second EL layer are positioned over the insulating layer and are provided to face each other. The common electrode is provided along the side surface of the first EL layer, the side surface of the second EL layer, and a top surface of the insulating layer. A width of the insulating layer is greater than or equal to 2 times and less than or equal to 4 times that of a distance between the first pixel electrode and the second pixel electrode.

公开(公告)号：US20230408595A1

公开(公告)日：2023-12-21

申请号：US18035992

申请日：2021-11-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA ,  Yosuke TSUKAMOTO ,  Takeshi OSADA ,  Hiroki INOUE ,  Kiyotaka KIMURA ,  Shunsuke SATO ,  Toshiki MIZUGUCHI

IPC: G01R31/389 ,  H01M10/48 ,  H01M10/42

CPC classification number: G01R31/389 ,  H01M10/486 ,  H01M10/4264 ,  H01M10/48

Abstract: Provided is a power storage system, a secondary battery control system, a secondary battery measurement circuit, or the like that consumes low power. Provided is a power storage system, a secondary battery control system, a secondary battery measurement circuit, or the like that is highly integrated. The power storage system includes a secondary battery and a measurement circuit; the measurement circuit includes a resistor, a capacitor, and an inductor; one terminal of the resistor is electrically connected to one electrode of the capacitor; the other terminal of the resistor is electrically connected to one terminal of the inductor; one terminal of the inductor is electrically connected to a positive electrode of the secondary battery; and the measurement circuit has a function of measuring impedance of the secondary battery by measuring current of the resistor.

公开(公告)号：US20230397437A1

公开(公告)日：2023-12-07

申请号：US18249415

申请日：2021-10-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Hitoshi KUNITAKE ,  Tatsuya ONUKI

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A semiconductor device that has a novel structure and includes a memory cell including a ferroelectric capacitor includes a first transistor (500A), a second transistor (500B), a first capacitor (600A), a second capacitor (600B), and a wiring (401). The first transistor is electrically connected to the first capacitor. The second transistor is electrically connected to the second capacitor. The wiring is positioned below the first transistor and the second transistor and is electrically connected to the first transistor or the second transistor. The first capacitor and the second capacitor each include a ferroelectric layer (630). The first capacitor and the second capacitor are placed on the same plane. The first capacitor and the second capacitor may include a region where they overlap with each other. Each of the first transistor and the second transistor preferably includes an oxide semiconductor in a channel. The ferroelectric layer preferably includes one or more selected from hafnium, zirconium, and Group III to IV elements.

公开(公告)号：US20230353110A1

公开(公告)日：2023-11-02

申请号：US17910057

申请日：2021-03-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Takayuki IKEDA ,  Shuji FUKAI ,  Shunpei YAMAZAKI

IPC: H03F3/72 ,  H03F3/217 ,  H01L29/786 ,  H01L27/06

CPC classification number: H03F3/72 ,  H03F3/2171 ,  H01L29/78693 ,  H01L27/0629 ,  H03F2203/7227

Abstract: A small semiconductor device is provided. A semiconductor device with low power consumption is provided. A semiconductor device with a high degree of integration is provided. The semiconductor device includes a first transistor, an insulating layer over the first transistor, a conductive layer, and a gate driver; part of the conductive layer is provided to be embedded in the insulating layer; the gate driver includes a second transistor and a third transistor; the second transistor and the third transistor are stacked and provided over the first transistor; the second transistor and the third transistor each contain a metal oxide in a channel formation region; one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to a gate of the first transistor through the conductive layer; the gate driver is supplied with a first potential and a second potential; and the gate driver has a function of selecting the first potential or the second potential and supplying the selected potential to the gate of the first transistor.

公开(公告)号：US20230283276A1

公开(公告)日：2023-09-07

申请号：US18016888

申请日：2021-07-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Shuhei NAGATSUKA

IPC: H03K17/687 ,  G06F7/544 ,  H01L29/786

CPC classification number: H03K17/687 ,  G06F7/5443 ,  H01L29/7869 ,  G06F2207/4824 ,  G06G7/16

Abstract: A semiconductor device with high arithmetic performance is provided. The semiconductor device employs the translinear principle, and the semiconductor device includes first to tenth transistors each including a metal oxide in a channel formation region and a first capacitor. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the third transistor is electrically connected to a second terminal of the second transistor and a gate of the second transistor through the first capacitor. The second terminal of the second transistor is electrically connected to first terminals of the fourth and the seventh transistors and gates of the fifth and the eighth transistors. A gate of the seventh transistor is electrically connected to first terminals of the fifth and the sixth transistors, and a gate of the tenth transistor is electrically connected to first terminals of the eighth and the ninth transistors.

公开(公告)号：US20230207567A1

公开(公告)日：2023-06-29

申请号：US17996516

申请日：2021-04-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuto YAKUBO ,  Shoki MIYATA ,  Akio SUZUKI ,  Takayuki IKEDA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1207 ,  H01L29/7869 ,  H01L29/78681

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a current-to-voltage conversion portion, a current switch portion, a voltage-to-current conversion portion, and a control portion. The current switch portion includes a first transistor. The voltage-to-current conversion portion includes a second transistor. The control portion includes a third transistor. The first transistor includes an oxide semiconductor in a channel formation region. The second transistor includes a nitride semiconductor in a channel formation region. The third transistor includes silicon in a channel formation region. The first transistor is provided over a first substrate. The second transistor and the third transistor are provided over a second substrate.

公开(公告)号：US20230090488A1

公开(公告)日：2023-03-23

申请号：US17904115

申请日：2021-02-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Seiichi YONEDA ,  Hiroki INOUE ,  Yusuke NEGORO ,  Takayuki IKEDA ,  Shunpei YAMAZAKI

IPC: H01L27/146 ,  H01L29/786

Abstract: A small-sized and highly functional imaging device is provided. The imaging device includes a photoelectric conversion device formed on a silicon substrate and a transistor including a channel formation region in a silicon epitaxial growth layer formed on the silicon substrate. The transistor provided in the epitaxial growth layer has favorable electrical characteristics, so that the imaging device with little noise can be formed. Since the transistor can be formed so as to have a region overlapping with the photoelectric conversion device, the imaging device can be downsized.

公开(公告)号：US20220384433A1

公开(公告)日：2022-12-01

申请号：US17770360

申请日：2020-10-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiko ISHIZU ,  Takayuki IKEDA ,  Atsushi MIYAGUCHI ,  Shunpei YAMAZAKI

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/66

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a p-channel transistor and an n-channel transistor provided over a silicon substrate. One of a source and a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source and a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source and the drain of the p-channel transistor is connected to the other of the source and the drain of the n-channel transistor. The p-channel transistor includes a first gate electrode and a first back gate electrode provided to face the first gate electrode with a first channel formation region therebetween. The first back gate electrode is formed using a region where an impurity element imparting conductivity is selectively introduced to the silicon substrate. The n-channel transistor is provided above a layer including the p-channel transistor.