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321 条记录 (耗时 0.03 秒)

    Semiconductor memory device including bit select circuit
    43.
    发明授权
    Semiconductor memory device including bit select circuit 有权
    包括位选择电路的半导体存储器件

    公开(公告)号：US06714451B2

    公开(公告)日：2004-03-30

    申请号：US10146021

    申请日：2002-05-16

    申请人： Tsukasa Ooishi ,  Hiroshi Kato

    发明人： Tsukasa Ooishi ,  Hiroshi Kato

    IPC分类号： G11C1616

    CPC分类号： G11C29/846 ,  G11C16/10 ,  G11C16/24 ,  G11C2216/30

    摘要： A plurality of nonvolatile memory cells having gates connected to a same word line, respectively, are connected in series, and connected to adjacent bit lines, respectively. When data is sequentially written to the plurality of nonvolatile memory cells, a bit line select circuit sequentially supplies a write potential outputted from a predetermined potential generation circuit to a plurality of bit lines. The bit line to which the write potential has been supplied once is kept to have the potential. Due to this, this nonvolatile semiconductor memory device can reduce an area occupied by a memory cell array.

    摘要翻译： 分别连接到相同字线的多个非易失性存储单元串联连接，分别连接到相邻的位线。 当数据被顺序写入多个非易失性存储单元时，位线选择电路将从预定电位产生电路输出的写电位顺序提供给多个位线。 写入电位一次的位线被保持为具有电位。 由此，这种非易失性半导体存储器件可以减少由存储单元阵列占据的面积。

    Semiconductor memory device
    45.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06807101B2

    公开(公告)日：2004-10-19

    申请号：US10326141

    申请日：2002-12-23

    申请人： Tsukasa Ooishi ,  Jun Ohtani ,  Hiroshi Kato

    发明人： Tsukasa Ooishi ,  Jun Ohtani ,  Hiroshi Kato

    IPC分类号： G11C1600

    CPC分类号： G11C16/3436 ,  G11C16/28

    摘要： A plurality of sense amplifiers are connected to a selected bit line. Each sense amplifier is supplied with a residual current corresponding to a current flowing in a memory cell and a reference current serving as a reference for a threshold voltage of the memory cell to sense the currents. Operations of the sense amplifiers are controlled such that different sense margins are provided to different sense amplifiers and a margin failure is detected according to coincidence/non-coincidence in logical level between output signals of the sense amplifiers. The address of a memory cell with the margin failure is registered. With such a construction, a threshold voltage defect of a non-volatile memory cell is compensated for to enable internal reading of memory cell data with correctness.

    摘要翻译： 多个读出放大器连接到选定的位线。 每个读出放大器被提供有对应于在存储单元中流动的电流的剩余电流和用作存储器单元的阈值电压的基准的参考电流以感测电流。 控制感测放大器的操作使得不同的感测余量被提供给不同的感测放大器，并且根据读出放大器的输出信号之间的逻辑电平中的符合/非重合检测到余量故障。 注册了具有余量故障的存储单元的地址。 通过这样的结构，可以补偿非易失性存储单元的阈值电压缺陷，以便能够正确地内部读取存储单元数据。

    Semiconductor integrated circuit device with split hierarchical power supply structure
    46.
    发明授权
    Semiconductor integrated circuit device with split hierarchical power supply structure 失效
    半导体集成电路器件具有分层分层电源结构

    公开(公告)号：US06407958B2

    公开(公告)日：2002-06-18

    申请号：US09817032

    申请日：2001-03-27

    申请人： Hiroshi Kato ,  Hideto Hidaka ,  Tsukasa Ooishi

    发明人： Hiroshi Kato ,  Hideto Hidaka ,  Tsukasa Ooishi

    IPC分类号： G11C700

    CPC分类号： G11C11/4074 ,  G11C8/12 ,  G11C29/846

    摘要： In an SDRAM, a column decoder is split into four blocks, and a specific predecode signal is allocated to each block. A sub power supply line is provided in correspondence to each block, and a P-channel MOS transistor, having a relatively high threshold voltage, rendered conductive in response to the corresponding predecode signal is connected between the sub power supply line and a main power supply line. A power supply potential is supplied to only a selected block, for reducing a leakage current.

    摘要翻译： 在SDRAM中，列解码器被分成四个块，并且将特定的预解码信号分配给每个块。 提供与每个块对应的副电源线，并且具有相对于相应的预解码信号导通的具有相对高阈值电压的P沟道MOS晶体管连接在副电源线和主电源 线。 电源电位只提供给选定的块，以减少漏电流。

    Non-volatile semiconductor memory device capable of high-speed data reading
    47.
    发明授权
    Non-volatile semiconductor memory device capable of high-speed data reading 失效
    能够进行高速数据读取的非易失性半导体存储器件

    公开(公告)号：US06744672B2

    公开(公告)日：2004-06-01

    申请号：US10283130

    申请日：2002-10-30

    申请人： Jun Ohtani ,  Tsukasa Ooishi ,  Hiroshi Kato

    发明人： Jun Ohtani ,  Tsukasa Ooishi ,  Hiroshi Kato

    IPC分类号： G11C1606

    CPC分类号： H01L21/28282 ,  G11C16/0475 ,  G11C16/28

    摘要： When a non-volatile memory cell which can store two bits per one memory cell and pass current bidirectionally is used, a bias power source potential is provided also to a bit line BL4 adjacent to two bit lines (BL2 and BL2) passing a sense current BL2 and BL3. Switch units are provided corresponding to each bit line for selectively connect to any one of a ground power source line, read power source line or bias power source line. The current flowing from a sense amplifier circuit to the adjacent bit line BL4 via adjacent memory cell can be reduced, and thus the current in the sense amplifier circuit is stabilized quickly. Accordingly, a non-volatile semiconductor memory device allows high-speed data reading operation.

    摘要翻译： 当使用可以每一个存储单元存储两个位并且双向通过电流的非易失性存储单元时，偏置电源电位也被提供给与通过检测电流的两个位线（BL2和BL2）相邻的位线BL4 BL2和BL3。 对应于每个位线提供开关单元，用于选择性地连接到地电源线，读取电源线或偏置电源线中的任何一个。 可以减少从读出放大器电路经由相邻存储单元流向相邻位线BL4的电流，从而可以快速稳定读出放大器电路中的电流。 因此，非易失性半导体存储器件允许高速数据读取操作。

    Thin film magnetic memory device and semiconductor integrated circuit device including the same as one of circuit blocks
    50.
    发明授权
    Thin film magnetic memory device and semiconductor integrated circuit device including the same as one of circuit blocks 有权
    薄膜磁存储器件和包括与电路块之一相同的半导体集成电路器件

    公开(公告)号：US07313014B2

    公开(公告)日：2007-12-25

    申请号：US11188089

    申请日：2005-07-25

    申请人： Tsukasa Ooishi

    发明人： Tsukasa Ooishi

    IPC分类号： G11C11/00

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/16

    摘要： Shape dummy cells that are designed to have the same dimensions and structures as MTJ memory cells are additionally provided in the peripheral portion of an MTJ memory cell array in which normal MTJ memory cells for storing data are arranged in a matrix. The MTJ memory cells and the shape dummy cells are sequentially arranged so as to have a uniform pitch throughout the entirety. Accordingly, non-uniformity between MTJ memory cells in the center portion and in border portions of the MTJ memory cell array, respectively, after manufacture due to high and low densities of the surrounding memory cells can be eliminated.

    摘要翻译： 被设计为具有与MTJ存储单元相同的尺寸和结构的形状虚设单元在MTJ存储单元阵列的外围部分中另外提供，其中用于存储数据的正常MTJ存储单元以矩阵形式布置。 依次布置MTJ存储单元和形状虚设单元，使整个整体具有均匀的间距。 因此，可以消除由于周围的存储单元的高密度和低密度而在制造之后的MTJ存储单元阵列的中心部分的MTJ存储单元和边界部分之间的不均匀性。