公开(公告)号：US07927949B2

公开(公告)日：2011-04-19

申请号：US12755532

申请日：2010-04-07

申请人： Yoshio Ozawa ,  Isao Kamioka ,  Junichi Shiozawa ,  Akihito Yamamoto ,  Ryota Fujitsuka ,  Yoshihiro Ogawa ,  Katsuaki Natori ,  Katsuyuki Sekine ,  Masayuki Tanaka ,  Daisuke Nishida

发明人： Yoshio Ozawa ,  Isao Kamioka ,  Junichi Shiozawa ,  Akihito Yamamoto ,  Ryota Fujitsuka ,  Yoshihiro Ogawa ,  Katsuaki Natori ,  Katsuyuki Sekine ,  Masayuki Tanaka ,  Daisuke Nishida

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.

摘要翻译： 一种半导体存储器件制造方法，包括在半导体衬底上形成浮置栅电极，在浮置栅电极上形成电极间绝缘膜，通过第一自由基氮化在电极间绝缘膜的表面上形成第一自由基氮化物膜， 第一自由基氮化物膜上的控制栅电极。

公开(公告)号：US20110012190A1

公开(公告)日：2011-01-20

申请号：US12888140

申请日：2010-09-22

申请人： Masayuki Tanaka ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Katsuyuki Sekine ,  Akihito Yamamoto ,  Katsuaki Natori ,  Yoshio Ozawa

发明人： Masayuki Tanaka ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Katsuyuki Sekine ,  Akihito Yamamoto ,  Katsuaki Natori ,  Yoshio Ozawa

IPC分类号： H01L29/68

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883

摘要： A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储层，形成在电荷存储层上的第二绝缘膜，以及形成在第二绝缘膜上的控制电极 ，所述第二绝缘膜包括下氮化硅膜，形成在所述下氮化硅膜上的下氧化硅膜，形成在所述下氧化硅膜上并含有金属元素的中间绝缘膜，所述中间绝缘膜具有相对电介质 大于7的常数，形成在中间绝缘膜上的上部氧化硅膜和形成在上部氧化硅膜上的上部氮化硅膜。

公开(公告)号：US07803682B2

公开(公告)日：2010-09-28

申请号：US11892282

申请日：2007-08-21

申请人： Katsuaki Natori ,  Masayuki Tanaka ,  Akihito Yamamoto

发明人： Katsuaki Natori ,  Masayuki Tanaka ,  Akihito Yamamoto

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.

摘要翻译： 半导体存储器件包括多个存储晶体管。 每个存储晶体管具有：浮栅电极; 电极间绝缘膜; 和控制栅电极。 浮栅电极在沿着位线方向的截面中包括第一导电膜，跨越第一导电膜的彼此相对的第一侧壁绝缘膜和设置在第一侧壁绝缘膜上的第二导电膜和 第一导电膜。 电极间绝缘膜设置在第二导电膜上。 控制栅电极包括设置在电极间绝缘膜上的第三导电膜和设置在第三导电膜上的第四导电膜。

公开(公告)号：US20100106368A1

公开(公告)日：2010-04-29

申请号：US12605873

申请日：2009-10-26

申请人： Seiji HIDAKA ,  Akihito Yamamoto

发明人： Seiji HIDAKA ,  Akihito Yamamoto

IPC分类号： B60G17/016

CPC分类号： B60G17/018 ,  B60G17/0165 ,  B60G17/08 ,  B60G2400/102 ,  B60G2400/252 ,  B60G2400/91 ,  B60G2500/10 ,  B60G2500/104 ,  B60G2600/11 ,  B60G2600/184 ,  B60G2600/1875 ,  B60G2800/162 ,  B60G2800/916

摘要： A damping force control apparatus includes a damping force control device controlling a damping force of a shock absorber provided between a sprung mass and an unsprung mass of each wheel of a vehicle, a detection device detecting at least an acceleration of the sprung mass in an up-down direction and a relative displacement between the sprung mass and the unsprung mass, a damping coefficient calculation device calculating a damping coefficient to be applied to the damping force control by the damping force control device based on detected results of the detection device, a sensed acceleration increment calculation device calculating a sensed acceleration increment corresponding to an increment of sense according to the Weber Fechner law on the basis of the detected results of the detection device, and a modification device modifying the damping coefficient in accordance with a sensed acceleration increment calculated by the sensed acceleration increment calculation device.

摘要翻译： 阻尼力控制装置包括：阻尼力控制装置，其控制设置在车辆的每个车轮的簧上质量块和非簧下质量之间的减震器的阻尼力;检测装置，至少检测弹簧质量的加速度 根据检测装置的检测结果，衰减系数计算装置计算由阻尼力控制装置对阻尼力控制施加的阻尼系数的阻尼系数计算装置， 加速度增量计算装置，根据检测装置的检测结果，根据韦伯费希勒定律计算对应于感觉增量的感测加速度增量;以及修正装置，根据由 感测加速度增量计算装置。

公开(公告)号：US20080149932A1

公开(公告)日：2008-06-26

申请号：US11946606

申请日：2007-11-28

申请人： Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshio Ozawa ,  Akihito Yamamoto

发明人： Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshio Ozawa ,  Akihito Yamamoto

IPC分类号： H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

摘要： A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上并且包括布置在半导体衬底上的多个存储单元的存储单元阵列，多个存储单元中的每一个包括设置在半导体衬底上的第一绝缘膜， 设置在所述第一绝缘膜上的电荷存储层，设置在所述电荷存储层上的第二绝缘膜，以及经由所述第二绝缘膜设置在所述电荷存储层上的含有金属或金属硅化物的控制电极， 的控制电极包括半导体，并且在存储单元的沟道宽度方向视图中不能容纳金属或金属硅化物。

公开(公告)号：US20080012061A1

公开(公告)日：2008-01-17

申请号：US11687758

申请日：2007-03-19

申请人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

发明人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

摘要翻译： 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮置栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

公开(公告)号：US07195930B2

公开(公告)日：2007-03-27

申请号：US11204079

申请日：2005-08-16

申请人： Takashi Shimizu ,  Akihito Yamamoto

发明人： Takashi Shimizu ,  Akihito Yamamoto

IPC分类号： H01L21/00

CPC分类号： C23C16/455 ,  C23C16/4405 ,  C23C16/52

摘要： A cleaning method for use in an apparatus for manufacturing a semiconductor device includes: measuring components and concentration of each component of gas in a process chamber of an apparatus for manufacturing a semiconductor device, or selected from a group including gas in the chamber, a process gas in a gas inlet pipe, and gas in a gas outlet pipe; performing a prescribed process on a substrate in the chamber, while adjusting the components and the concentration of each component of the process gas, and of an atmosphere in the chamber, on the basis of the values measured, and taking the substrate from the chamber after the process is subjected; and generating and applying a cleaning gas on the basis of the values measured, the cleaning gas having such components and such concentration as to remove residues.

摘要翻译： 一种用于制造半导体器件的设备的清洁方法，包括：测量半导体器件制造装置的处理室中的气体成分和浓度，或者选自包括室中的气体的组中的气体成分和浓度， 进气管中的气体和气体出口管中的气体; 在室内的基板上进行规定的处理，同时基于所测量的值调节处理气体的各成分和室内的气氛的成分和浓度，并从室后取出基板 该过程受到影响 基于所测量的值产生和施加清洁气体，具有这种组分的清洁气体和除去残留物的浓度。

公开(公告)号：US20070026149A1

公开(公告)日：2007-02-01

申请号：US11494735

申请日：2006-07-28

申请人： Takashi Shimizu ,  Kazuo Saki ,  Kazuhiro Nishiki ,  Akihito Yamamoto ,  Shinji Mori

发明人： Takashi Shimizu ,  Kazuo Saki ,  Kazuhiro Nishiki ,  Akihito Yamamoto ,  Shinji Mori

IPC分类号： C23C16/00

CPC分类号： H01L21/31662 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/3144 ,  H01L22/20

摘要： In a process of annealing an insulating film such as a silicon oxide film (SiO2) or a silicon oxynitride film (SiON) provided in a processing chamber 6 within an atmosphere of an inert gas 2 guided from a first mass flow controller 3 via a gas inlet 7, an amount of SiO sublimated from the surface of the insulating film in the processing chamber 6 is measured by a mass spectrometer 10, and an amount of oxygen gas 4 guided to the processing chamber 6 from a second mass flow controller 5 is controlled by a controller 1 so that the SiO concentration does not exceed a predetermined level, thereby effectively controlling the SiO sublimation. As a result, the film deterioration caused by the SiO sublimation is prevented and an insulating film having a high reliability and good characteristics can be formed in a controllable manner.

摘要翻译： 在将惰性气体2的气氛2中引导的处理室6中设置的氧化硅膜（SiO 2/2）或氧氮化硅膜（SiON）等绝缘膜退火的工序中， 通过气体入口7的第一质量流量控制器3，通过质谱仪10测量从处理室6中的绝缘膜的表面升华的SiO的量，并且从处理室6中引导到处理室6的量的氧气 第二质量流量控制器5由控制器1控制，使得SiO浓度不超过预定水平，从而有效地控制SiO升华。 结果，防止了由SiO升华引起的膜劣化，并且可以以可控的方式形成具有高可靠性和良好特性的绝缘膜。

公开(公告)号：US20060046441A1

公开(公告)日：2006-03-02

申请号：US11211745

申请日：2005-08-26

申请人： Kiyotaka Miyano ,  Akihito Yamamoto ,  Yoshihiko Saito

发明人： Kiyotaka Miyano ,  Akihito Yamamoto ,  Yoshihiko Saito

IPC分类号： H01L21/20

CPC分类号： H01L29/7834 ,  C30B25/16 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66628

摘要： According to the present invention, there is provided a selectivity monitoring method in a selective film growth method of selectively growing a film in a predetermined region on a semiconductor substrate, comprising: selectively growing the film on a surface of the semiconductor substrate while measuring temperature of the surface of the semiconductor substrate by at least one pyrometer placed in a non-contact state above the surface of the semiconductor substrate; and determining that selectivity of the growth of the film has decreased, when the temperature changes from a predetermined value or changes from a predetermined angle in a graph showing change of the temperature during film formation.

摘要翻译： 根据本发明，提供了选择性膜生长方法中选择性地生长半导体衬底上预定区域中的膜的选择性监测方法，包括：在半导体衬底的表面上选择性地生长膜，同时测量温度 所述半导体衬底的表面通过在所述半导体衬底的表面上方处于非接触状态的至少一个高温计; 并且当温度从预定值变化或者在显示成膜期间温度变化的曲线图中从预定角度改变时，确定膜生长的选择性已经降低。

公开(公告)号：US5750436A

公开(公告)日：1998-05-12

申请号：US485506

申请日：1995-06-07

申请人： Kenichi Yamaga ,  Yuichi Mikata ,  Akihito Yamamoto

发明人： Kenichi Yamaga ,  Yuichi Mikata ,  Akihito Yamamoto

IPC分类号： C23C16/34 ,  C23C16/44 ,  C23C16/455 ,  C23C16/54 ,  C23C16/56 ,  H01L21/31 ,  H01L21/316

CPC分类号： C23C16/4409 ,  C23C16/345 ,  C23C16/455 ,  C23C16/54 ,  C23C16/56

摘要： An Si.sub.3 N.sub.4 layer is formed on a surface of a wafer, which is an object to be processed, at a high temperature of, for example, 780.degree. C., using a vertical thermal processing apparatus having a reaction tube of a double-wall structure comprising an inner tube and an outer tube in which a predetermined reduced-pressure status is maintained within the reaction tube while a reaction gas comprising, for example, SiH.sub.2 Cl.sub.2 and NH.sub.3 is made to flow from an inner side to an outer side of the inner tube by the action of a first gas supply pipe and first exhaust pipe provided in the thermal processing apparatus. Next, the temperature in the interior of the reaction tube is raised to, for example, 1000.degree. C., a reaction gas comprising, for example, H.sub.2 O vapor and HCl is made to flow from the outer side to the inner side of the inner tube by the action of a second gas supply pipe and second exhaust pipe, and an SiO.sub.2 layer is formed by the oxidation of the surface of the Si.sub.3 N.sub.4 layer formed on the surface of the wafer, under normal-pressure conditions. The use of a combined chamber enables the implementation of film formation and either oxidation or diffusion processing without having to remove the object to be processed from the reaction tube, and thus prevents the intrusion of a natural oxide layer or the incorporation of particles into a thin film structure of, for example, SiO.sub.2 and Si.sub.3 N.sub.4 layers used as a multi-layer insulating film for devices such as DRAMs.