公开(公告)号：US20120231564A1

公开(公告)日：2012-09-13

申请号：US13415270

申请日：2012-03-08

申请人： KYOUNG-WOO LEE ,  Hong-Jae Shin ,  Woo-Jin Jang

发明人： KYOUNG-WOO LEE ,  Hong-Jae Shin ,  Woo-Jin Jang

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

摘要翻译： 公开了一种用于半导体器件中的蚀刻工艺的监测TEG。 TEG包括衬底上的蚀刻停止层和设置在蚀刻停止层上的要蚀刻的靶层。 要蚀刻的目标层包括通过蚀刻待蚀刻的目标层的一部分形成的第一开口部分和通过蚀刻待蚀刻的目标层的另一部分而形成的第二开口部分。 第二开口部的深度比第一开口部小。 可以测量通过第一部分蚀刻工艺形成的部分接触孔的深度。

公开(公告)号：US08248352B2

公开(公告)日：2012-08-21

申请号：US12318301

申请日：2008-12-24

申请人： Jin-Ho Kim ,  Hong-Jae Shin

发明人： Jin-Ho Kim ,  Hong-Jae Shin

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2320/0223

摘要： A driving circuit of a liquid crystal display includes: a timing controller to output a gate control signal and a data control signal to control driving of a gate driving unit and a data driving unit and to output digital video data; a pair of gate driving units to be alternately driven by using at least one frame as a period to supply gate signals to gate lines of a liquid crystal panel in-response to the gate control signal; and a data driving unit to supply pixel signals to data lines of the liquid crystal panel in response to the data control signal. Degradation of characteristics of transistors constituting each gate driver can be prevented.

摘要翻译： 液晶显示器的驱动电路包括：时序控制器，用于输出栅极控制信号和数据控制信号，以控制栅极驱动单元和数据驱动单元的驱动并输出数字视频数据; 一对栅极驱动单元，通过使用至少一个帧作为周期来交替驱动，以响应于栅极控制信号向液晶面板的栅极线提供栅极信号; 以及数据驱动单元，用于响应于数据控制信号将像素信号提供给液晶面板的数据线。 可以防止构成每个栅极驱动器的晶体管的特性的降低。

公开(公告)号：US07410896B2

公开(公告)日：2008-08-12

申请号：US11328954

申请日：2006-01-09

申请人： Hong-Jae Shin

发明人： Hong-Jae Shin

IPC分类号： H01L21/4763

CPC分类号： H01L24/05 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05552

摘要： A low-k dielectric film is formed on an entire surface of a substrate having a pad region and a circuit region. A resist pattern is formed on the low-k dielectric film, and an opening is formed in the low-k dielectric film of the pad region using the resist pattern as a mask. A silicon oxide film having strength higher than the low-k dielectric film is formed in the opening using liquid-phase deposition method. Wirings are formed in the silicon oxide film of the pad region and in the low-k dielectric film of the circuit region using damascene method.

摘要翻译： 在具有焊盘区域和电路区域的衬底的整个表面上形成低k电介质膜。 在低k电介质膜上形成抗蚀剂图案，并且使用抗蚀剂图案作为掩模，在焊盘区域的低k电介质膜中形成开口。 使用液相沉积法在开口中形成强度高于低k电介质膜的氧化硅膜。 使用镶嵌方法，在焊盘区域的氧化硅膜和电路区域的低k电介质膜中形成布线。

公开(公告)号：US20060110915A1

公开(公告)日：2006-05-25

申请号：US11328954

申请日：2006-01-09

申请人： Hong-Jae Shin

发明人： Hong-Jae Shin

IPC分类号： H01L21/4763

CPC分类号： H01L24/05 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05552

摘要： A low-k dielectric film is formed on an entire surface of a substrate having a pad region and a circuit region. A resist pattern is formed on the low-k dielectric film, and an opening is formed in the low-k dielectric film of the pad region using the resist pattern as a mask. A silicon oxide film having strength higher than the low-k dielectric film is formed in the opening using liquid-phase deposition method. Wirings are formed in the silicon oxide film of the pad region and in the low-k dielectric film of the circuit region using damascene method.

摘要翻译： 在具有焊盘区域和电路区域的衬底的整个表面上形成低k电介质膜。 在低k电介质膜上形成抗蚀剂图案，并且使用抗蚀剂图案作为掩模，在焊盘区域的低k电介质膜中形成开口。 使用液相沉积法在开口中形成强度高于低k电介质膜的氧化硅膜。 使用镶嵌方法，在焊盘区域的氧化硅膜和电路区域的低k电介质膜中形成布线。

公开(公告)号：US07015589B2

公开(公告)日：2006-03-21

申请号：US10806341

申请日：2004-03-23

申请人： Hong-Jae Shin

发明人： Hong-Jae Shin

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/05 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05552

摘要： A low-k dielectric film is formed on an entire surface of a substrate having a pad region and a circuit region. A resist pattern is formed on the low-k dielectric film, and an opening is formed in the low-k dielectric film of the pad region using the resist pattern as a mask. A silicon oxide film having strength higher than the low-k dielectric film is formed in the opening by liquid-phase deposition. Wirings are formed in the silicon oxide film of the pad region and in the low-k dielectric film of the circuit region using the damascene method.

摘要翻译： 在具有焊盘区域和电路区域的衬底的整个表面上形成低k电介质膜。 在低k电介质膜上形成抗蚀剂图案，并且使用抗蚀剂图案作为掩模，在焊盘区域的低k电介质膜中形成开口。 通过液相沉积在开口中形成强度高于低k电介质膜的氧化硅膜。 使用镶嵌方法，在焊盘区域的氧化硅膜和电路区域的低k电介质膜中形成布线。

公开(公告)号：US20060009065A1

公开(公告)日：2006-01-12

申请号：US11174864

申请日：2005-07-05

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

IPC分类号： H01R4/24

CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

摘要翻译： 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有阶梯部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

公开(公告)号：US20060003574A1

公开(公告)日：2006-01-05

申请号：US11099534

申请日：2005-04-06

申请人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

发明人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808

摘要： A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.

摘要翻译： 公开了一种使用双镶嵌工艺形成通孔接触结构的方法。 根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。 牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。 在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。 根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。 在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

公开(公告)号：US20050176236A1

公开(公告)日：2005-08-11

申请号：US11049730

申请日：2005-02-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/3205 ,  H01L21/02 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/02063 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76835

摘要： The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

摘要翻译： 本发明公开了一种制造用于半导体器件的互连线的方法。 该方法包括在半导体衬底上形成层间绝缘层。 通过层间绝缘层形成通孔。 形成通孔填充材料以填充通孔。 在通孔填充材料上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为蚀刻掩模对通孔填充材料和层间绝缘层进行各向异性蚀刻以形成沟槽。 使用两次湿式蚀刻工艺去除通孔填充材料的剩余部分。 在去除通孔填充材料的剩余部分之后，在通孔和沟槽中形成导电层图案。

公开(公告)号：US20050161821A1

公开(公告)日：2005-07-28

申请号：US11028515

申请日：2005-01-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76829

摘要： Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

摘要翻译： 公开了形成互连线和互连线结构的方法。 该方法包括在半导体衬底上形成层间绝缘层，其中层间绝缘层由碳掺杂的低k电介质层形成。 在层间绝缘层上形成氧化阻隔层。 在氧化阻挡层上形成氧化物覆盖层。 通孔位于氧化物覆盖层，氧化阻挡层和层间绝缘层中。 导电层图案形成在通孔内。