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41.发明申请Semiconductor Devices, Methods of Manufacturing Thereof, and Image Sensor Devices 有权半导体器件，其制造方法和图像传感器设备公开(公告)号：US20150115389A1
公开(公告)日：2015-04-30
申请号：US14326268
申请日：2014-07-08
Inventor： Chun-Chieh Chuang , Dun-Nian Yaung , Feng-Chi Hung , Min-Feng Kao , Jeng-Shyan Lin , Chun-Ming Su , Ching-Chun Wang
IPC: H01L27/146 , H01L21/48 , H01L23/48
CPC classification number: H01L27/14636 , H01L21/486 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/585 , H01L27/14634 , H01L27/1464 , H01L27/14687 , H01L27/1469 , H01L2224/08145 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device includes a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. A guard structure is disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region. A portion of the guard structure is disposed within a substrate of the semiconductor chip.
Abstract translation: 公开了半导体器件，其制造方法和图像传感器器件。 在一些实施例中，半导体器件包括包括阵列区域，外围区域和设置在其中的通孔的半导体芯片。 保护结构设置在半导体芯片之间的阵列区域和通孔之间，或贯穿通孔与外围区域的一部分之间。 保护结构的一部分设置在半导体芯片的基板内。
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公开(公告)号：US08969991B2
公开(公告)日：2015-03-03
申请号：US14178084
申请日：2014-02-11
Inventor： Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Keng-Yu Chou , Shuang-Ji Tsai , Min-Feng Kao
IPC: H01L21/00 , H01L27/146 , H01L31/0216 , H01L31/18
CPC classification number: H01L27/14685 , G02B1/11 , H01L27/1462 , H01L27/14623 , H01L27/14636 , H01L27/1464 , H01L27/14645 , H01L31/02161 , H01L31/1868 , Y02E10/50 , Y02P70/521
Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.
Abstract translation: BSI图像传感器和方法。 在一个实施例中，提供具有传感器阵列和周边区域并具有前侧和后侧表面的基板; 底部抗反射涂层（BARC）在传感器阵列区域和外围区域的上方形成在第一厚度的背侧上; 在BARC上形成第一介电层; 形成金属屏蔽; 从所述传感器阵列区域上方选择性地去除所述金属屏蔽件; 从所述传感器阵列区域上方选择性地去除所述第一介电层，其中所述BARC的第一厚度的一部分也被去除，并且在选择性地去除所述第一介电层的过程中所述BARC的第一厚度的剩余部分保留; 在BARC的其余部分和金属屏蔽层之上形成第二电介质层; 以及在所述第二介电层上形成钝化层。
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公开(公告)号：US20140264883A1
公开(公告)日：2014-09-18
申请号：US13866802
申请日：2013-04-19
Inventor： Shu-Ting Tsai , Jeng-Shyan Lin , Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung
IPC: H01L23/522 , H01L23/532
CPC classification number: A61N1/3931 , A61N1/3987 , H01L21/76898 , H01L23/481 , H01L23/53238 , H01L23/53257 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2224/08145 , H01L2224/80894 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/1431 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
Abstract translation: 半导体器件包括结合在第二芯片上的第一芯片。 第一芯片包括形成在第一IMD层中的第一衬底和第一互连部件。 第二芯片包括形成在第二IMD层中的第二基板和第二互连部件。 该装置还包括形成在第一衬底和第一IMD层内的第一导电插塞，其中第一导电插塞耦合到第一互连部件和通过第一衬底和第一IMD层形成的第二导电插塞，并且部分地穿过 所述第二IMD层，其中所述第二导电插塞耦合到第二互连部件。
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公开(公告)号：US20140264508A1
公开(公告)日：2014-09-18
申请号：US14143848
申请日：2013-12-30
Inventor： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Feng-Chi Hung , Shuang-Ji Tsai , Jeng-Shyan Lin , Shu-Ting Tsai , Wen-I Hsu
IPC: H01L27/146 , H01L31/02
CPC classification number: H01L27/14636 , H01L27/1461 , H01L27/1462 , H01L27/14634 , H01L27/14641 , H01L27/14643 , H01L27/14685 , H01L27/14689 , H01L27/1469 , H01L31/02005
Abstract: The present disclosure provides an embodiment of an image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
Abstract translation: 本公开提供了一种图像传感器结构的实施例，其包括具有多个成像传感器的第一半导体衬底; 形成在所述第一半导体衬底上的第一互连结构; 具有逻辑电路的第二半导体衬底; 形成在所述第二半导体衬底上的第二互连结构，其中所述第一和第二半导体衬底以第一和第二互连结构夹在所述第一和第二半导体衬底之间的结构结合在一起; 以及从第一互连结构延伸到第二互连结构的背侧深度接触（BDCT）特征，从而将逻辑电路电耦合到图像传感器。
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公开(公告)号：US20140035013A1
公开(公告)日：2014-02-06
申请号：US14057140
申请日：2013-10-18
Inventor： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Wen-De Wang
IPC: H01L27/146
CPC classification number: H01L27/146 , H01L27/14632 , H01L27/14636 , H01L27/1464 , H01L27/14687
Abstract: Provided is a method of fabricating an image sensor device. The method includes providing a first substrate having a radiation-sensing region disposed therein. The method includes providing a second substrate having a hydrogen implant layer, the hydrogen implant layer dividing the second substrate into a first portion and a second portion. The method includes bonding the first portion of the second substrate to the first substrate. The method includes after the bonding, removing the second portion of the second substrate. The method includes after the removing, forming one or more microelectronic devices in the first portion of the second substrate. The method includes forming an interconnect structure over the first portion of the second substrate, the interconnect structure containing interconnect features that are electrically coupled to the microelectronic devices.
Abstract translation: 提供了一种制造图像传感器装置的方法。 该方法包括提供其中设置有辐射感测区域的第一基板。 该方法包括提供具有氢注入层的第二衬底，氢注入层将第二衬底分成第一部分和第二部分。 该方法包括将第二衬底的第一部分接合到第一衬底。 该方法包括在接合之后，去除第二衬底的第二部分。 该方法包括在去除之后，在第二衬底的第一部分中形成一个或多个微电子器件。 该方法包括在第二基板的第一部分上形成互连结构，所述互连结构包含电耦合到微电子器件的互连特征。
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Patent Agency Ranking
公开(公告)号：US11798916B2
公开(公告)日：2023-10-24
申请号：US16048777
申请日：2018-07-30
Inventor： Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Chia-Chieh Lin , U-Ting Chen
IPC: H01L23/48 , H01L25/065 , H01L25/00 , H01L21/768 , H01L23/00 , H01L23/532
CPC classification number: H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/92 , H01L25/50 , H01L21/76805 , H01L21/76831 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L24/80 , H01L24/82 , H01L2224/24145 , H01L2224/80896 , H01L2224/821 , H01L2224/8203 , H01L2224/82106 , H01L2224/9202 , H01L2224/9212 , H01L2225/06541 , H01L2924/0002 , H01L2224/8203 , H01L2224/821 , H01L2224/9212 , H01L2224/80001 , H01L2224/82
Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
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公开(公告)号：US10090353B2
公开(公告)日：2018-10-02
申请号：US15608722
申请日：2017-05-30
Inventor： Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Tzu-Hsuan Hsu , Feng-Chi Hung , Min-Feng Kao
IPC: H01L31/00 , H01L27/146
Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.
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公开(公告)号：US09887182B2
公开(公告)日：2018-02-06
申请号：US15598209
申请日：2017-05-17
Inventor： Ju-Shi Chen , Cheng-Ying Ho , Chun-Chieh Chuang , Sheng-Chau Chen , Shih Pei Chou , Hui-Wen Shen , Dun-Nian Yaung , Ching-Chun Wang , Feng-Chi Hung , Shyh-Fann Ting
CPC classification number: H01L25/105 , H01L25/50 , H01L2225/1041 , H01L2225/1082
Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 Å. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges. Improved planarity of wafers presented for hybrid bonding results in improved bond uniformity for 3DIC devices formed thereby.
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公开(公告)号：US20170309603A1
公开(公告)日：2017-10-26
申请号：US15598209
申请日：2017-05-17
Inventor： Ju-Shi Chen , Cheng-Ying Ho , Chun-Chieh Chuang , Sheng-Chau Chen , Shih Pei Chou , Hui-Wen Shen , Dun-Nian Yaung , Ching-Chun Wang , Feng-Chi Hung , Shyh-Fann Ting
CPC classification number: H01L25/105 , H01L25/50 , H01L2225/1041 , H01L2225/1082
Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 Å. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges. Improved planarity of wafers presented for hybrid bonding results in improved bond uniformity for 3DIC devices formed thereby.
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公开(公告)号：US09764153B2
公开(公告)日：2017-09-19
申请号：US13866802
申请日：2013-04-19
Inventor： Shu-Ting Tsai , Jeng-Shyan Lin , Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung
IPC: H01L23/522 , H01L21/768 , H01L23/00 , H01L25/00 , A61N1/39 , H01L23/48 , H01L23/532 , H01L27/06 , H01L27/146
CPC classification number: A61N1/3931 , A61N1/3987 , H01L21/76898 , H01L23/481 , H01L23/53238 , H01L23/53257 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2224/08145 , H01L2224/80894 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/1431 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
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