公开(公告)号：US11709203B2

公开(公告)日：2023-07-25

申请号：US17690821

申请日：2022-03-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Sundarrajan Rangachari ,  Prashanth Saraf

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3181 ,  G01R31/317

CPC classification number: G01R31/318307 ,  G01R31/31726 ,  G01R31/31727 ,  G01R31/31813 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/31708

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

公开(公告)号：US11555853B2

公开(公告)日：2023-01-17

申请号：US17093702

申请日：2020-11-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Nikita Naresh

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317

Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.

公开(公告)号：US11521698B2

公开(公告)日：2022-12-06

申请号：US17002813

申请日：2020-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Nikita Naresh ,  Prathyusha Teja Inuganti ,  Rakesh Channabasappa Yaraduyathinahalli ,  Aravinda Acharya ,  Jasbir Singh ,  Naveen Ambalametil Narayanan

IPC: G11C29/38 ,  G11C17/00 ,  G11C29/00 ,  G11C11/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/04 ,  G11C29/08 ,  G11C14/00 ,  G06F12/06 ,  G06F9/4401

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

公开(公告)号：US11519964B2

公开(公告)日：2022-12-06

申请号：US17353882

申请日：2021-06-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Wilson Pradeep

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

公开(公告)号：US11194645B2

公开(公告)日：2021-12-07

申请号：US16737548

申请日：2020-01-08

Applicant: Texas Instruments Incorporated

Inventor： Aravinda Acharya ,  Wilson Pradeep ,  Prakash Narayanan

IPC: G06F11/07 ,  G01R31/3185 ,  G01R31/317 ,  G11C29/56 ,  G11C29/12 ,  G11C29/20 ,  G11C29/32 ,  G11C29/50 ,  G11C29/14 ,  G06F11/26 ,  G01R31/14 ,  G11C29/10 ,  G11C29/36

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

公开(公告)号：US20210364569A1

公开(公告)日：2021-11-25

申请号：US17396079

申请日：2021-08-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin A, Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G01R31/3177 ,  G01R31/3185

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US11119152B2

公开(公告)日：2021-09-14

申请号：US16780119

申请日：2020-02-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G06F11/00 ,  G01R31/3177 ,  G01R31/3185

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US11073557B2

公开(公告)日：2021-07-27

申请号：US16406858

申请日：2019-05-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Wilson Pradeep

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

公开(公告)号：US20210215757A1

公开(公告)日：2021-07-15

申请号：US17217391

申请日：2021-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rajesh Kumar Mittal ,  Rajat Mehrotra

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

公开(公告)号：US10983161B2

公开(公告)日：2021-04-20

申请号：US16380182

申请日：2019-04-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rajesh Kumar Mittal ,  Rajat Mehrotra

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3177

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.