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公开(公告)号:US20240361533A1
公开(公告)日:2024-10-31
申请号:US18769241
申请日:2024-07-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Tsung SHIH , Chewn-Pu JOU , Stefan RUSU , Felix Ying-Kit TSUI , Lan-Chou CHO
Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a method for forming an optical coupler, includes: forming an insulation layer on a semiconductor substrate; epitaxially growing a semiconductor material on the insulation layer to form a semiconductor layer; etching, according to a predetermined pattern, the semiconductor layer to form: an array of etched holes in the semiconductor layer to form a grating region, a first taper structure extending from a first side of the grating region, wherein a shape of the first taper structure in the semiconductor layer is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region, and a second taper structure extending from a second side of the grating region, wherein a shape of the second taper structure in the semiconductor layer is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region, wherein the first side and the second side are substantially perpendicular to each other; and depositing a dielectric material into the array of etched regions to form an array of scattering elements in the semiconductor layer, wherein the scattering elements are arranged to form a two-dimensional (2D) grating.
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公开(公告)号:US20220373854A1
公开(公告)日:2022-11-24
申请号:US17881434
申请日:2022-08-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Huan-Neng CHEN , Chewn-Pu JOU , Lan-Chou CHO , Feng-Wei KUO
Abstract: In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
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公开(公告)号:US20220155524A1
公开(公告)日:2022-05-19
申请号:US17097270
申请日:2020-11-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Weiwei SONG , Chan-Hong CHERN , Chewn-Pu JOU , Stefan RUSU , Min-Hsiang HSU
Abstract: An optical system with different optical coupling device configurations and a method of fabricating the same are disclosed. An optical system includes a substrate, a waveguide disposed on the substrate, an optical fiber optically coupled to the waveguide, and an optical coupling device disposed between the optical fiber and the waveguide. The optical coupling device configured to optically couple the optical fiber to the waveguide. The optical coupling device includes a dielectric layer disposed on the substrate, a semiconductor tapered structure disposed in a first horizontal plane within the dielectric layer, and a multi-tip dielectric structure disposed in a second horizontal plane within the dielectric layer. The first and second horizontal planes are different from each other
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公开(公告)号:US20220035223A1
公开(公告)日:2022-02-03
申请号:US17503095
申请日:2021-10-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Lan-Chou CHO , Chewn-Pu JOU , Min-Hsiang HSU
IPC: G02F1/225
Abstract: Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. In some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. The phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. Each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. The combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.
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公开(公告)号:US20210271147A1
公开(公告)日:2021-09-02
申请号:US16804522
申请日:2020-02-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Lan-Chou CHO , Chewn-Pu JOU , Min-Hsiang HSU
IPC: G02F1/225
Abstract: Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. In some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. The phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. Each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. The combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.
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公开(公告)号:US20200057351A1
公开(公告)日:2020-02-20
申请号:US16532270
申请日:2019-08-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Huan-Neng CHEN , Chewn-Pu JOU , Lan-Chou CHO , Feng-Wei KUO , Yutong WU
Abstract: In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
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公开(公告)号:US20190288692A1
公开(公告)日:2019-09-19
申请号:US16429774
申请日:2019-06-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Feng Wei KUO , Chewn-Pu JOU , Huan-Neng CHEN , Lan-Chou CHO , Robert Bogdan STASZEWSKI , Seyednaser POURMOUSAVIAN
Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.
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公开(公告)号:US20180287775A1
公开(公告)日:2018-10-04
申请号:US16002970
申请日:2018-06-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Huan-Neng CHEN , William Wu SHEN , Lan-Chou CHO , Feng-Wei KUO , Chewn-Pu JOU
CPC classification number: H04L7/0331 , H04L7/0041 , H04L7/042 , H04L27/00 , H04L27/227
Abstract: A device, a circuit and a method are disclosed herein. The device includes a data receiving circuit and an oscillating signal generator. The data receiving circuit is configured to output a first output signal, a second output signal, and a phase error signal according to an oscillating signal and a modulated signal, in which the phase error signal indicates a phase difference between the oscillating signal and the modulated signal. The oscillating signal generator is configured to delay a phase of a first reference signal according to the phase error signal, to generate the oscillating signal.
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公开(公告)号:US20170207147A1
公开(公告)日:2017-07-20
申请号:US15474700
申请日:2017-03-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Wen-Shiang LIAO , Chewn-Pu JOU
IPC: H01L23/485 , H01L23/00
CPC classification number: H01L23/485 , H01L21/568 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5223 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L27/0805 , H01L28/60 , H01L28/90 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/24195 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2224/94 , H01L2924/19041 , H01L2924/19105 , H01L2224/83005 , H01L2224/214
Abstract: A semiconductor device includes a plurality of redistribution layers, a dielectric layer, and a conductive structure. The redistribution layers are formed overlying a device die to provide an electrical connection between the device die and an external connector in a package. The dielectric layer is arranged between the redistribution layers to form a capacitor structure. The conductive structure is formed and coupled between the device die and the redistribution layers.
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公开(公告)号:US20170146959A1
公开(公告)日:2017-05-25
申请号:US15422523
申请日:2017-02-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Lan-Chou CHO , Chewn-Pu JOU , Feng-Wei KUO , Huan-Neng CHEN
IPC: G04F10/00 , H03K5/131 , H03K5/1534
CPC classification number: G04F10/005 , H03K5/131 , H03K5/135 , H03K5/1534 , H03K5/24 , H03K2005/00058 , H03K2005/00071
Abstract: A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.
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