公开(公告)号：US20240088016A1

公开(公告)日：2024-03-14

申请号：US18511438

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L21/0214 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/60 ,  H01L21/31053

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.

公开(公告)号：US20230389437A1

公开(公告)日：2023-11-30

申请号：US18361832

申请日：2023-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H10N50/01 ,  G11C11/16 ,  H10N50/80 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H10N50/01 ,  G11C11/161 ,  H10N50/80 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

Abstract: A semiconductor device includes a substrate with a metal line embedded in the substrate, a dielectric layer disposed on the substrate, a bottom electrode via extending through the dielectric layer and landing on a top surface of the metal line, a bottom electrode disposed on a top surface of the bottom electrode via, a magnetic tunneling junction stack disposed on a top surface of the bottom electrode, and a top electrode disposed on the magnetic tunneling junction stack. A lower portion of the bottom electrode via includes a first metal, and an upper portion of the bottom electrode via includes a second metal that is different from the first metal.

公开(公告)号：US20230369199A1

公开(公告)日：2023-11-16

申请号：US18359011

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen ,  Hsiao Ching-Wen ,  Yao-Chun Chuang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L21/76843 ,  H01L28/40 ,  H01L23/528 ,  H01L28/91 ,  H10B12/033

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

公开(公告)号：US11778918B2

公开(公告)日：2023-10-03

申请号：US16998911

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/01 ,  G11C11/161 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A method for manufacturing a memory device includes forming a via trench in a substrate and forming a via in the via trench. A lower portion of the via includes a first metal and an upper portion of the via includes a second metal that is different from the first metal. The method further includes forming a magnetic tunneling junction over the via and forming a top electrode over the magnetic tunneling junction.

公开(公告)号：US11728262B2

公开(公告)日：2023-08-15

申请号：US17470680

申请日：2021-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen ,  Hsiao Ching-Wen ,  Yao-Chun Chuang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H10B12/00 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76843 ,  H01L23/528 ,  H01L28/40 ,  H01L28/91 ,  H10B12/033

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

公开(公告)号：US20230187392A1

公开(公告)日：2023-06-15

申请号：US18166960

申请日：2023-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Dian-Hau Chen

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/05647 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/1357 ,  H01L2224/13024 ,  H01L2224/02381

Abstract: A semiconductor structure includes a first dielectric layer over a metal line and a redistribution layer (RDL) over the first dielectric layer. The RDL is electrically connected to the metal line. The RDL has a curved top surface and a footing feature, where the footing feature extends laterally from a side surface of the RDL. A second dielectric layer is disposed over the RDL, where the second dielectric layer also has a curved top surface.

公开(公告)号：US20230145953A1

公开(公告)日：2023-05-11

申请号：US17589500

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Wen-Chiung Tu ,  Yuan-Yang Hsiao ,  Kai Tak Lam ,  Chen-Chiu Huang ,  Zhiqiang Wu ,  Dian-Hau Chen

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/35121

Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.

公开(公告)号：US11581276B2

公开(公告)日：2023-02-14

申请号：US16941308

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Dian-Hau Chen

IPC: H01L23/00

Abstract: A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump.

公开(公告)号：US11502182B2

公开(公告)日：2022-11-15

申请号：US16872166

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsin Yang ,  Yen-Ming Chen ,  Feng-Cheng Yang ,  Tsung-Lin Lee ,  Wei-Yang Lee ,  Dian-Hau Chen

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/49 ,  G06F30/392 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  G06F119/18

Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

公开(公告)号：US20220310903A1

公开(公告)日：2022-09-29

申请号：US17377737

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Kai-Wen Cheng ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.