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    SEMICONDCUTOR PACKAGES
    41.
    发明申请
    SEMICONDCUTOR PACKAGES 审中-公开

    公开(公告)号：US20190148341A1

    公开(公告)日：2019-05-16

    申请号：US16228799

    申请日：2018-12-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

    IPC: H01L25/065 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

    Abstract: Semiconductor packages are provided. One of the semiconductor packages includes a first chip, a second chip, a first adhesive layer, a second adhesive layer and a molding layer. The first adhesive layer is disposed on a first surface of the first chip and a second adhesive layer is disposed on a second surface of the second chip, wherein the first adhesive layer and the second adhesive layer have different thickness, and a total thickness of the first chip and the first adhesive layer is substantially equal to a total thickness of the second chip and the second adhesive layer. The molding layer encapsulates the first chip, the second chip, the first adhesive layer and the second adhesive layer.

    STACKED VIA STRUCTURE AND METHOD OF FABRICATING THE SAME
    42.
    发明申请
    STACKED VIA STRUCTURE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190131235A1

    公开(公告)日：2019-05-02

    申请号：US15879457

    申请日：2018-01-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

    IPC: H01L23/522 ,  H01L21/66 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00

    Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

    Semiconductor device and method of manufacturing the same
    44.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US10204870B2

    公开(公告)日：2019-02-12

    申请号：US15289173

    申请日：2016-10-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Zi-Jheng Liu ,  Jo-Lin Lan ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

    IPC: H01L23/544 ,  H01L23/538 ,  H01L23/00 ,  H01L23/58 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56

    Abstract: A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip region, and a scribe region surroundingly defined around the seal ring region, the semiconductor structure including: a semiconductor chip in the chip region; and a molding compound disposed around the semiconductor chip and distributed in the chip region, the seal ring region and the scribe region; forming an insulating film over the chip region of the semiconductor structure and the seal ring region of the semiconductor structure; forming a seal ring over the seal ring region of the semiconductor structure and laterally adjacent to the insulating film, in which the seal ring has an exposed lateral surface facing away from the insulating film; and forming a protective layer that defines a substantially smooth and inclined lateral surface over the exposed lateral surface of the seal ring.

    INTEGRATED CIRCUIT PACKAGE AND METHOD OF FABRICATING THE SAME
    45.
    发明申请
    INTEGRATED CIRCUIT PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20180301389A1

    公开(公告)日：2018-10-18

    申请号：US15486306

    申请日：2017-04-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Zi-Jheng Liu ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/11 ,  H01L23/544 ,  H01L21/56 ,  H01L25/00 ,  H01L21/321 ,  H01L21/683

    Abstract: An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner. The redistribution circuit structure is disposed on the planar top surface of the insulating encapsulation, the top surfaces of the conductive vias and the patterned dielectric liner. The redistribution circuit structure is electrically connected to the conductive vias.

    Chuck Design and Method for Wafer
    49.
    发明申请
    Chuck Design and Method for Wafer 有权

    公开(公告)号：US20240395595A1

    公开(公告)日：2024-11-28

    申请号：US18788481

    申请日：2024-07-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Ming-Tan Lee ,  Hung-Jui Kuo

    IPC: H01L21/683 ,  B25B11/00 ,  H01L21/687 ,  H01L23/00

    Abstract: An apparatus for securing a wafer includes a chuck, at least one O-ring disposed on the chuck, a vacuum system connected to the chuck, such that the vacuum system comprises a plurality of vacuum holes through the chuck connected to one or more vacuum pumps, and a controller configured to control the height of the at least one O-ring relative to the top surface of the chuck. The controller is connected to pressure sensors capable of detecting a vacuum. The at least one O-ring may include a plurality of O-rings.

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