公开(公告)号：US11901190B2

公开(公告)日：2024-02-13

申请号：US15967100

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yuan Tseng ,  Yu-Tien Shen ,  Wei-Liang Lin ,  Chih-Ming Lai ,  Kuo-Cheng Ching ,  Shi Ning Ju ,  Li-Te Lin ,  Ru-Gun Liu

IPC: H01L21/311 ,  H01L21/32 ,  H01L23/528 ,  H01L21/3213

CPC classification number: H01L21/31105 ,  H01L21/32 ,  H01L21/32139 ,  H01L23/528

Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

公开(公告)号：US11791161B2

公开(公告)日：2023-10-17

申请号：US17114070

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Ya-Wen Yeh ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Ru-Gun Liu ,  Kuei-Shun Chen

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/306 ,  G03F7/20 ,  G03F7/11

CPC classification number: H01L21/0273 ,  G03F7/09 ,  H01L21/0337 ,  H01L21/311 ,  G03F7/11 ,  G03F7/20 ,  H01L21/0274 ,  H01L21/306

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.

公开(公告)号：US11776850B2

公开(公告)日：2023-10-03

申请号：US17652761

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Chen ,  Li-Te Lin ,  Chao-Hsien Huang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1025 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

公开(公告)号：US11515423B2

公开(公告)日：2022-11-29

申请号：US16880864

申请日：2020-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao Kuo ,  Jung-Hao Chang ,  Chao-Hsien Huang ,  Li-Te Lin ,  Kuo-Cheng Ching

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02

Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

公开(公告)号：US20220336611A1

公开(公告)日：2022-10-20

申请号：US17471859

申请日：2021-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fo-Ju LIN ,  Fang-Wei Lee ,  Chih-Long Chiang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/311

Abstract: The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.

公开(公告)号：US20220297234A1

公开(公告)日：2022-09-22

申请号：US17832832

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: B23K26/348 ,  H01L21/3115 ,  B23K26/067 ,  B23K26/06 ,  H01L21/311

Abstract: A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.

公开(公告)号：US11424341B2

公开(公告)日：2022-08-23

申请号：US16937901

申请日：2020-07-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/027 ,  H01L29/423 ,  H01L21/308 ,  H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3213

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.

公开(公告)号：US11351635B2

公开(公告)日：2022-06-07

申请号：US16653401

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: B23K26/348 ,  H01L21/3115 ,  B23K26/067 ,  B23K26/06 ,  H01L21/311

Abstract: A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.

公开(公告)号：US20210257478A1

公开(公告)日：2021-08-19

申请号：US17306316

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US11094556B2

公开(公告)日：2021-08-17

申请号：US16383539

申请日：2019-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen Yeh ,  Yu-Tien Shen ,  Shih-Chun Huang ,  Po-Chin Chang ,  Wei-Liang Lin ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu

IPC: H01L21/3213 ,  H01L21/66

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.