公开(公告)号：US11508582B2

公开(公告)日：2022-11-22

申请号：US16927031

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Uei Jang ,  Ya-Yi Tsai ,  Ryan Chia-Jen Chen ,  An Chyi Wei ,  Shu-Yuan Ku

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02

Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

公开(公告)号：US20220310820A1

公开(公告)日：2022-09-29

申请号：US17805552

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Huang Huang ,  Ming-Jhe Sie ,  Yih-Ann Lin ,  An Chyi Wei ,  Ryan Chia-Jen Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764 ,  H01L29/45 ,  H01L21/285

Abstract: A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

公开(公告)号：US20220181217A1

公开(公告)日：2022-06-09

申请号：US17652712

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chun Chen ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ya-Yi Tsai ,  I-Wei Yang

IPC: H01L21/8238 ,  H01L27/092

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

公开(公告)号：US20210242192A1

公开(公告)日：2021-08-05

申请号：US17218284

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ming-Ching Chang

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/06

Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.

公开(公告)号：US20210134973A1

公开(公告)日：2021-05-06

申请号：US16806280

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Huang Huang ,  Ming-Jhe Sie ,  Yih-Ann Lin ,  An Chyi Wei ,  Ryan Chia-Jen Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/285 ,  H01L21/764 ,  H01L29/45 ,  H01L29/78

Abstract: A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

公开(公告)号：US20210090958A1

公开(公告)日：2021-03-25

申请号：US17114082

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Uei Jang ,  Chen-Huang Huang ,  Ryan Chia-Jen Chen ,  Shiang-Bau Wang ,  Shu-Yuan Ku

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78

Abstract: A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

公开(公告)号：US10535654B2

公开(公告)日：2020-01-14

申请号：US15904835

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Chun-Liang Lai ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3105

Abstract: A semiconductor device includes a substrate, first and second fins protruding out of the substrate, and first and second high-k metal gates (HK MG) disposed over the first and second fins, respectively. From a top view, the first and second fins are arranged lengthwise along a first direction, the first and second HK MG are arranged lengthwise along a second direction generally perpendicular to the first direction, and the first and second HK MG are aligned along the second direction. In a cross-sectional view cut along the second direction, the first HK MG has a first sidewall that is slanted from top to bottom towards the second HK MG, and the second HK MG has a second sidewall that is slanted from top to bottom towards the first HK MG. Methods for producing the semiconductor device are also disclosed.

公开(公告)号：US10276449B1

公开(公告)日：2019-04-30

申请号：US15821904

申请日：2017-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Shu-Uei Jang ,  Yu-Wen Wang ,  Ryan Chia-Jen Chen ,  An-Chyi Wei

IPC: H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure includes providing a substrate having a first fin structure and a second fin structure that are capped by a patterned hard mask structure. A liner layer and an overlying insulating layer are formed between the first and second fin structures. A multi-step etching process including a first step of selectively removing the patterned hard mask structure and a second step of in-situ and selectively removing a portion of the insulating layer to form an isolation feature is performed. The process gas used in the multi-step etching process includes a first etching gas and a second etching gas. The flow rate of the first etching gas is greater than that of the second etching gas in the first step and the flow rate of the first etching gas is less than that of the second etching gas in the second step.

公开(公告)号：US09704974B2

公开(公告)日：2017-07-11

申请号：US14688885

申请日：2015-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei Chang ,  An-Shen Chang ,  Eric Chih-Fang Liu ,  Ryan Chia-Jen Chen ,  Chia-Tai Lin ,  Chih-Tang Peng

IPC: H01L29/66 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3086

Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.

公开(公告)号：US20240363431A1

公开(公告)日：2024-10-31

申请号：US18766881

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chieh-Ning Feng ,  Chun-Liang Lai ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/7834 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.