公开(公告)号：US20050117390A1

公开(公告)日：2005-06-02

申请号：US10776249

申请日：2004-02-12

申请人： Kenji Tsuchida

发明人： Kenji Tsuchida

IPC分类号： G11C11/15 ,  G11C11/14

CPC分类号： G11C11/14

摘要： A semiconductor integrated circuit device has a semiconductor substrate comprising a first region extending along the edge and a second region surrounded by the first region. Memory cell arrays are provided in the second region, and comprising a plurality of cells having an MTJ element. Gate transistors are provided in the first region, and have a current path having a first terminal connected with a bit line, which is a signal read path from the cells, and a second terminal opposite to the first terminal. Data buses are connected with the same number of the second terminals. A connection control circuit is provided in the second region, and connects selected two of the data buses to first and second output terminals, respectively. An amplifier circuit is provided in the first region, and amplifies a potential difference in accordance with signals outputted from the first and second output terminals.

公开(公告)号：US20050047202A1

公开(公告)日：2005-03-03

申请号：US10728917

申请日：2003-12-08

申请人： Yuui Shimizu ,  Yoshihisa Iwata ,  Kenji Tsuchida ,  Tatsuya Kishi

发明人： Yuui Shimizu ,  Yoshihisa Iwata ,  Kenji Tsuchida ,  Tatsuya Kishi

IPC分类号： G01R31/28 ,  G11C11/15 ,  G11C29/04 ,  G11C29/12 ,  G11C11/00

CPC分类号： G11C11/16 ,  G11C29/12

摘要： An MRAM has an internal test circuit. This test circuit detects a bit in a memory cell array, which has a shift in write characteristics, as a defective bit by using a method of applying a one-axis write current along an axis of hard magnetization.

公开(公告)号：US06807088B2

公开(公告)日：2004-10-19

申请号：US10423936

申请日：2003-04-28

申请人： Kenji Tsuchida

发明人： Kenji Tsuchida

IPC分类号： G11C1100

CPC分类号： G11C11/15

摘要： Reference cells are provided in a memory cell array. When the data is read, the data in the reference cells are inverted, thereby preventing the data in the selected cell from changing. This makes it possible to decrease the number of write operations and realize a high-speed read operation and lower power consumption.

摘要翻译： 参考单元被提供在存储单元阵列中。 当读取数据时，参考单元中的数据被反转，从而防止所选单元格中的数据改变。 这使得可以减少写入操作的数量并实现高速读取操作和降低功耗。

公开(公告)号：US06404698B1

公开(公告)日：2002-06-11

申请号：US09496032

申请日：2000-01-21

申请人： Tsuneo Inaba ,  Shinichiro Shiratake ,  Kenji Tsuchida

发明人： Tsuneo Inaba ,  Shinichiro Shiratake ,  Kenji Tsuchida

IPC分类号： G11C800

CPC分类号： G11C29/80

摘要： There is provided a semiconductor memory device which comprises a plurality of memory cells, a plurality of bit lines connected with the plurality of memory cells, a plurality of word lines connected with the plurality of memory cells, a plurality of data line pairs, a plurality of transfer gates for effecting controlled connection of the plurality of bit lines with the plurality of data lines, a plurality of column select lines for controlling conductibility of the plurality of the transfer gates, and a column select line drive circuit for simultaneously selecting and driving at least two of the plurality of column select lines corresponding to one-time column address input from the outside of the chip.

摘要翻译： 提供了一种半导体存储器件，其包括多个存储器单元，与多个存储单元连接的多个位线，与多个存储单元连接的多个字线，多个数据线对，多个 用于实现多个位线与多条数据线的受控连接的多个传输门，用于控制多个传送门的导电性的多个列选择线，以及用于同时选择和驱动的列选择线驱动电路 对应于从芯片外部输入的一次列地址的多个列选择线中的至少两个。

公开(公告)号：US6108254A

公开(公告)日：2000-08-22

申请号：US150782

申请日：1993-11-12

申请人： Yohji Watanabe ,  Kenji Tsuchida

发明人： Yohji Watanabe ,  Kenji Tsuchida

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/407

CPC分类号： G11C7/106 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22

摘要： A Dynamic Random Access Memory (DRAM) in which a data input/output buffer is connected between first data lines and second data lines. An equalizing circuit and a data latch circuit are connected to the second data lines. The equalizing circuit maintains the second data lines in reset condition, during normal operation. It temporarily releases the second data lines from the reset condition, in response to an output from an address-transition detecting circuit, thereby to transfer the data from the data input/output buffer. The data latch circuit latches the data transferred to the second data lines, in response to the output from the address-transition detecting circuit.

摘要翻译： 动态随机存取存储器（DRAM），其中数据输入/输出缓冲器连接在第一数据线和第二数据线之间。 均衡电路和数据锁存电路连接到第二数据线。 均衡电路在正常工作期间将第二条​​数据线保持在复位状态。 它响应于地址转换检测电路的输出暂时从复位状态释放第二数据线，从而从数据输入/输出缓冲器传送数据。 数据锁存电路根据地址转换检测电路的输出锁存传送到第二数据线的数据。

公开(公告)号：US6097660A

公开(公告)日：2000-08-01

申请号：US53511

申请日：1998-04-02

申请人： Kenji Tsuchida ,  Shinichiro Shiratake ,  Tsuneo Inaba

发明人： Kenji Tsuchida ,  Shinichiro Shiratake ,  Tsuneo Inaba

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C8/12 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C5/025 ,  G11C11/4097 ,  G11C8/12

摘要： A semiconductor memory device comprises a plurality of memory banks each having a plurality of memory cell arrays and a plurality of sense amplifiers such that the memory cell arrays and the sense amplifiers are alternately disposed in a first direction, the memory banks being disposed in a second direction perpendicular to the first direction, a plurality of row decoders respectively provided in the first direction for the plurality of memory banks, a column decoder provided in the second direction with respect to the plurality of memory banks, a plurality of first data lines respectively provided in the second direction for the plurality of memory banks, and connected with the plurality of sense amplifiers in accordance with a signal outputted from the column decoder, a plurality of second data lines provided in the second direction, penetrating through the plurality of memory banks, and shared by the plurality of first data lines disposed for the plurality of memory banks, and a plurality of switching elements each having a first end connected to one of the plurality of first data lines and a second end connected to one of the plurality of second data lines, and controlled by a bank activation signal of a memory bank corresponding to the first data line connected to the first ends.

摘要翻译： 半导体存储器件包括多个存储器组，每个存储器组具有多个存储单元阵列和多个读出放大器，使得存储单元阵列和读出放大器交替地沿第一方向设置，存储体设置在第二 分别设置在多个存储体的第一方向的多个行解码器，相对于多个存储体设置在第二方向上的列解码器，分别设置有多个第一数据线 在所述多个存储体的第二方向上，并且根据从所述列解码器输出的信号与所述多个读出放大器连接;沿着所述第二方向设置的穿过所述多个存储体的多个第二数据线， 并且由为多个存储体设置的多个第一数据线和plu共享 开关元件的强度各自具有连接到多个第一数据线之一的第一端和连接到所述多条第二数据线之一的第二端，并且由对应于第一数据的存储体的存储体激活信号控制 线连接到第一端。

公开(公告)号：US6094390A

公开(公告)日：2000-07-25

申请号：US72724

申请日：1998-05-06

申请人： Tsuneo Inaba ,  Shinichiro Shiratake ,  Kenji Tsuchida

发明人： Tsuneo Inaba ,  Shinichiro Shiratake ,  Kenji Tsuchida

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： H01L27/10897 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18

摘要： A semiconductor memory device with a semiconductor substrate and a plurality of element regions formed in the semiconductor is shown. The semiconductor memory device further includes at least one column gate and at least one equalizer in which they are formed as a set in at least one of the element regions.

摘要翻译： 示出了半导体衬底和半导体中形成的多个元件区的半导体存储器件。 半导体存储器件还包括至少一个列栅极和至少一个均衡器，其中它们在至少一个元件区域中形成为一组。

公开(公告)号：US5933051A

公开(公告)日：1999-08-03

申请号：US714291

申请日：1996-09-18

申请人： Kenji Tsuchida ,  Yoshio Okada

发明人： Kenji Tsuchida ,  Yoshio Okada

IPC分类号： H03F3/343 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  G05F3/02

CPC分类号： G05F3/242 ,  G05F3/24 ,  G11C5/147

摘要： A constant voltage generating device comprises a reference voltage generating circuit, a constant-current circuit unit and a current-to-voltage converting circuit unit. The reference voltage generating circuit generates a desired reference voltage. The constant-current circuit unit comprises a differential error amplifier to which the reference voltage generated by the reference voltage generating circuit is input as a reference potential, a first current controlling MOS transistor having a gate electrode to which an output of the differential amplifier is input, and a standard resistor serially connected to the first current controlling MOS transistor. The constant-current circuit unit generates a reference current to control a differential amplifier so that a constant current can be caused to flow therethrough. The current-to-voltage converting unit comprises a second current controlling MOS transistor constituting a current mirror together with the first current controlling MOS transistor of the constant-current circuit unit, and a current-to-voltage converting MOS transistor serially connected to the second current controlling MOS transistor and constituting a current mirror together with an active element unit current controlling MOS transistor of the differential amplifier.

摘要翻译： 恒压发生装置包括参考电压产生电路，恒流电路单元和电流 - 电压转换电路单元。 参考电压产生电路产生期望的参考电压。 恒流电路单元包括差分误差放大器，由基准电压产生电路产生的参考电压输入到该参考电压作为参考电位;第一电流控制MOS晶体管，具有输入差分放大器的输入端的栅电极 以及串联连接到第一电流控制MOS晶体管的标准电阻器。 恒流电路单元产生参考电流以控制差分放大器，使得可以使恒定电流流过。 电流 - 电压转换单元包括与恒流电路单元的第一电流控制MOS晶体管一起构成电流镜的第二电流控制MOS晶体管和串联连接到第二电流控制MOS晶体管的电流 - 电压转换MOS晶体管 电流控制MOS晶体管，并与差分放大器的有源元件单元电流控制MOS晶体管一起构成电流镜。

公开(公告)号：US5859805A

公开(公告)日：1999-01-12

申请号：US832818

申请日：1997-04-04

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

公开(公告)号：US5644525A

公开(公告)日：1997-07-01

申请号：US272284

申请日：1994-07-08

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02 ,  G11C11/407 ,  G11C11/413

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

摘要翻译： 动态半导体存储器件由沿着多个位线对排列的多个动态存储器单元和与多个位线对相关联的多个动态读出放大器组成，每个读出放大器具有连接的一对MOS晶体管 到相应的一对位线。 在一个实施例中，读出放大器之一的第一和第二晶体管和与其相邻的另一个读出放大器的第一和第二晶体管位于由两个相邻的位线对限定的区域内。 每个位线对具有在与第二方向垂直的第一方向上延伸的第一和第二位线，其中源极和漏极区域形成在半导体衬底中，使得读出放大器的晶体管每四位排列一个 线在第二个方向。