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57 条记录 (耗时 0.026 秒)

    Chip type varistor
    43.
    发明授权
    Chip type varistor 失效
    片式压敏电阻

    公开(公告)号：US5324986A

    公开(公告)日：1994-06-28

    申请号：US901750

    申请日：1992-06-22

    申请人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

    发明人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

    IPC分类号： H01C7/10 ,  H01C7/112 ,  H01L23/053 ,  H01L23/14 ,  H01L23/15

    CPC分类号： H01C7/10 ,  H01C7/112

    摘要： A chip type varistor in which first and second inner electrodes are embedded in a sintered body obtained by laminating a plurality of semiconductor ceramics layers so as not to be overlapped with each other in the direction of thickness of the ceramics layers, respective one edges of the first and second inner electrodes are led out to one and the other of a pair of side surfaces opposed to each other of the sintered body and are electrically connected to outer electrodes formed on the pair of side surfaces of the sintered body, respectively, a non-connected type inner electrode which is not electrically connected to the above described outer electrodes is embedded in the sintered body, and the non-connected type inner electrode is arranged so as to be overlapped with the first and second inner electrodes while being separated by the semiconductor ceramics layer.

    摘要翻译： 一种芯片型变阻器，其中第一和第二内部电极嵌入在通过层叠多个半导体陶瓷层而不是在陶瓷层的厚度方向上彼此不重叠而获得的烧结体中， 第一和第二内部电极被引出到烧结体彼此相对的一对侧表面中的一个和另一个，并且分别与形成在烧结体的一对侧表面上的外部电极电连接， 不与上述外部电极电连接的连接型内部电极嵌入在烧结体中，非连接型内部电极配置成与第一和第二内部电极重叠，同时被 半导体陶瓷层。

    Monolithic type varistor
    44.
    发明授权
    Monolithic type varistor 失效
    单片类型变量

    公开(公告)号：US5119062A

    公开(公告)日：1992-06-02

    申请号：US615369

    申请日：1990-11-19

    申请人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

    发明人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

    IPC分类号： H01C7/10

    CPC分类号： H01C7/10

    摘要： A monolithic type varistor in which a plurality of inner electrodes are arranged in a sintered body composed of semiconductor ceramics so as to be overlapped with each other while being separated by semiconductor ceramic layers. The plurality of inner electrodes are electrically connected to first and second outer electrodes formed on both end surfaces of the sintered body. One or more non-connected type inner electrodes are arranged between adjacent ones of the plurality of inner electrodes and are not electrically connected to the outer electrodes, each of the non-connected type inner electrodes being spaced apart from each adjacent inner electrode or non-connected type inner electrode while being separated therefrom by a semiconductor ceramic layer. Voltage non-linearity is obtained by Schottky barriers formed at the interface of the inner electrode and the semiconductor ceramic layer and the interface of the non-connected type inner electrode and the semiconductor ceramic layer. The value of the number of grain boundaries between semiconductor particles in at least one semiconductor ceramic layer is two or less.

    摘要翻译： 一种单片型压敏电阻，其中多个内部电极被布置在由半导体陶瓷组成的烧结体中，以便在被半导体陶瓷层分离的同时彼此重叠。 多个内部电极电连接到形成在烧结体的两个端面上的第一和第二外部电极。 一个或多个非连接型内部电极布置在多个内部电极的相邻的内部电极之间，并且不与外部电极电连接，每个非连接型内部电极与每个相邻的内部电极或非电连接的内部电极间隔开， 连接型内部电极，同时由半导体陶瓷层分离。 通过在内部电极和半导体陶瓷层的界面处形成的肖特基势垒以及非连接型内部电极和半导体陶瓷层的界面获得电压非线性。 至少一个半导体陶瓷层中的半导体粒子之间的晶界数的值为2以下。

    Laminated varistor
    45.
    发明授权
    Laminated varistor 失效
    层压变阻器

    公开(公告)号：US5075665A

    公开(公告)日：1991-12-24

    申请号：US404838

    申请日：1989-09-08

    申请人： Hiroaki Taira ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Yutaka Shimahara

    发明人： Hiroaki Taira ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Yutaka Shimahara

    IPC分类号： H01C1/14 ,  H01C7/102

    CPC分类号： H01C7/102 ,  H01C1/14

    摘要： Respective first end portions of first and second internal electrodes are exposed at respective end surfaces of a varistor body, which is in the form of a rectangular parallelepiped. These end surfaces of the varistor body are covered with low resistance parts which include ceramic material in order to prevent the internal electrodes from decomposition. External electrodes are formed on the low resistance parts, so as, to be electrically connected with corresponding ones of the internal electrodes through the low resistance parts.

    摘要翻译： 第一和第二内部电极的相应的第一端部暴露在可变形电阻体的相应的端面上，该非线性电阻体是矩形平行六面体的形式。 可变电阻体的这些端面由包括陶瓷材料的低电阻部分覆盖，以防止内部电极分解。 外部电极形成在低电阻部分上，以便通过低电阻部分与相应的内部电极电连接。

    RADIO BASE STATION, RADIO COMMUNICATION SYSTEM, AND CONTROL METHOD
    49.
    发明申请
    RADIO BASE STATION, RADIO COMMUNICATION SYSTEM, AND CONTROL METHOD 有权
    无线电基站，无线电通信系统和控制方法

    公开(公告)号：US20130072201A1

    公开(公告)日：2013-03-21

    申请号：US13700122

    申请日：2011-05-27

    申请人： Kazutaka Nakamura ,  Chiharu Yamazaki ,  Taku Nakayama ,  Shingo Joko ,  Yoshimasa Kusano

    发明人： Kazutaka Nakamura ,  Chiharu Yamazaki ,  Taku Nakayama ,  Shingo Joko ,  Yoshimasa Kusano

    IPC分类号： H04W28/08

    CPC分类号： H04W16/08 ,  H04W36/22 ,  H04W72/0426 ,  H04W72/0486 ,  H04W92/20

    摘要： A radio base station (eNB1), which is used in a radio communication system that can autonomously adjust, based on load information transmitted/received between radio base stations, the radio base station parameters used for defining coverage, comprises: a network communication unit (140) that can receive, from another radio base station, first load information indicating the load level of the other radio base station and that can transmit, to the other radio base station, a request for transmission of second load information the information amount of which is greater than that of the first load information; and a control unit (120) that, when the load level of the other radio base station indicated by the received first load information satisfies a given condition, controls such that the request for transmission of the second load information is transmitted to the other radio base station.

    摘要翻译： 一种无线电基站（eNB1），用于能够根据无线基站之间发送/接收的负载信息自主调整用于定义覆盖的无线基站参数的无线通信系统，包括：网络通信单元 140），其可以从另一个无线电基站接收首先加载指示另一个无线电基站的负载水平的信息，并且可以向另一个无线电基站发送第二负载信息的发送请求，该第二负载信息的信息量 大于第一载荷信息; 以及控制单元（120），当由所接收的第一负载信息指示的另一无线电基站的负载水平满足给定条件时，控制使得第二负载信息的发送请求被发送到另一无线电基站 站。

    Ultraviolet sensor
    50.
    发明授权
    Ultraviolet sensor 有权
    紫外线传感器

    公开(公告)号：US08372681B2

    公开(公告)日：2013-02-12

    申请号：US13569422

    申请日：2012-08-08

    申请人： Kazutaka Nakamura ,  Yoshihiro Ito

    发明人： Kazutaka Nakamura ,  Yoshihiro Ito

    IPC分类号： H01L21/00

    CPC分类号： H01L31/109 ,  H01L31/18

    摘要： A diode type ultraviolet sensor having a layered-structure body including a conductive layer composed of a sintered ceramic body having conductivity and a semiconductor layer composed of an oxide semiconductor including ZnO. The semiconductor layer is disposed on a principal surface of the conductive layer and forms a heterojunction with the conductive layer. The ultraviolet sensor is used in such a condition that the semiconductor layer is positioned at a light-receiving side irradiated by ultraviolet rays. The semiconductor layer is preferably composed of a sintered body. The sintered body serving as the conductive layer and sintered body serving as the semiconductor layer are preferably formed by co-firing. Terminal electrodes are provided on a principal surface and the other principal surface of the layered-structure body, respectively.

    摘要翻译： 一种二极管型紫外线传感器，具有层叠结构体，其包括由具有导电性的烧结陶瓷体构成的导电层和由包含ZnO的氧化物半导体构成的半导体层。 半导体层设置在导电层的主表面上并与导电层形成异质结。 紫外线传感器在半导体层位于受紫外线照射的受光面的状态下使用。 半导体层优选由烧结体构成。 用作导电层的烧结体和用作半导体层的烧结体优选通过共烧成形。 端子电极分别设置在分层结构体的主表面和另一个主表面上。