公开(公告)号：US06512272B1

公开(公告)日：2003-01-28

申请号：US09685038

申请日：2000-10-10

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： H01L2976

CPC分类号： H01L29/1041 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： An FET and DRAM using a plurality of such FETs wherein each transistor has a body region of a first conductivity type including a relatively high VT region and relatively low VT region, the high VT region disposed contiguous with the low VT region. A pair of source/drain regions of opposite conductivity type are disposed on a pair of opposing sides of each of the low VT region. The transistor includes a gate oxide over the body region and a gate electrode over the gate oxide and spaced from the body region. The body region is p-doped or n-doped with the high VT region more heavily doped than the remainder of the body. In a further embodiment, the FET includes a body region of a first conductivity type which includes a relatively low VT region and a first pair of relatively high VT regions on a first pair of opposing sides of the body. A pair of source/drain regions of opposite conductivity type are disposed on a second pair of opposing sides of each of the low VT region. A gate oxide is disposed over the body region and a gate electrode is disposed over the gate oxide and spaced from the body region.

摘要翻译： 使用多个这样的FET的FET和DRAM，其中每个晶体管具有包括相对较高的VT区和相对低的VT区的第一导电类型的体区，与低VT区邻接设置的高VT区。 一对相反导电类型的源极/漏极区域设置在每个低VT区域的一对相对侧上。 晶体管包括在主体区域上的栅极氧化物和位于栅极氧化物上并与体区间隔开的栅电极。 身体区域是p型掺杂或n掺杂的，具有比身体其余部分更重掺杂的高VT区域。 在另一个实施例中，FET包括第一导电类型的主体区域，其在主体的第一对相对侧上包括相对低的VT区域和第一对相对较高的VT区域。 一对相反导电类型的源极/漏极区域设置在每个低VT区域的第二对相对侧上。 栅极氧化物设置在身体区域上，并且栅电极设置在栅极氧化物上方并与身体区域间隔开。

公开(公告)号：US06351176B1

公开(公告)日：2002-02-26

申请号：US09395027

申请日：1999-09-13

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： G05F110

CPC分类号： G11C7/062 ,  G11C8/10 ,  H03K19/01707

摘要： A circuit (300) employing metal-oxide-semiconductor (MOS) devices is disclosed. The circuit (300) includes a circuit portion (302) that provides a circuit function, and a body voltage adjust portion (304) which alters the body potential of the transistors within the circuit portion (302). By adjusting the body potentials of the circuit portion (300) transistors, the speed at which the circuit portion (300) can perform its function is increased. A decoder circuit embodiment (800) and sense amplifier embodiments (1200, 1300, 1500, 1600, 1700, 1800, 1900 and 2000) are also disclosed.

摘要翻译： 公开了采用金属氧化物半导体（MOS）器件的电路（300）。 电路（300）包括提供电路功能的电路部分（302）和改变电路部分（302）内的晶体管的体电位的体电压调节部分（304）。 通过调节电路部分（300）晶体管的体电位，电路部分（300）可以执行其功能的速度增加。 还公开了解码器电路实施例（800）和读出放大器实施例（1200,1300,1500,1600,1700,1800,1900和2000）。

公开(公告)号：US6114945A

公开(公告)日：2000-09-05

申请号：US852982

申请日：1997-05-08

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： G06F7/02 ,  G06F7/50

CPC分类号： G06F7/02

摘要： A programmable fast comparison circuit for determining whether the result of a logic operation on two operands is the same as a specified number in advance of the completion of the actual operation includes four fast compare units coupled to each operand signal pairs of the same degree of significance for identifying possible result signal pairs of the same degree of significance. Each fast compare circuit generates a positive signal when a result signal pair is possible based on the corresponding operand bit signal pairs. Control signals determined by the specified number signal pair of the same degree of significance is used to activate one of the four fast compare circuits with the corresponding result signal pair. When the fast compare circuit activated by the control signals is a circuit generating a positive signal, the positive signal is transmitted to a combinatorial circuit. When a positive signal is transmitted by all the sets of fast compare circuits (and one result signal bit is specifically identified with a positive signal applied to the combinatorial circuit), the result number is identical with the specified number and an answer-correct signal is generated. By using the symmetry of the possible result bit signal pairs, the four fast compare circuits for each result signal pair can be reduced to two fast compare circuits. In another embodiment, N kill/generate/propagate circuits can perform a programmable fast comparison for logic operations involving two N length operands.

摘要翻译： 一种可编程快速比较电路，用于确定在两个操作数之间的逻辑运算的结果是否与实际操作完成之前的指定数量相同，包括耦合到具有相同程度的意义的每个操作数信号对的四个快速比较单元 用于识别具有相同程度重要性的可能的结果信号对。 当基于对应的操作数位信号对可以得到结果信号对时，每个快速比较电路产生一个正信号。 由具有相同程度的指定数量信号对确定的控制信号用于使用相应的结果信号对激活四个快速比较电路中的一个。 当由控制信号激活的快速比较电路是产生正信号的电路时，正信号被发送到组合电路。 当所有快速比较电路组发送正信号（并且一个结果信号位被特定地用施加到组合电路的正信号识别）时，结果编号与指定的数字相同，并且应答信号是 生成。 通过使用可能的结果位信号对的对称性，每个结果信号对的四个快速比较电路可以减少到两个快速比较电路。 在另一个实施例中，N个停止/生成/传播电路可以对涉及两个N个长度操作数的逻辑运算执行可编程的快速比较。

公开(公告)号：US6096612A

公开(公告)日：2000-08-01

申请号：US70213

申请日：1998-04-30

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L29/42368 ,  H01L21/76237 ,  H01L21/823468

摘要： A structure and a method for fabricating integrated circuits are disclosed in which narrow trench isolation structures (36) are formed between active regions (38) of an integrated circuit (10). A silicon nitride layer is deposited, patterned and etched to provide nitride mask (16) having spaces (20) which are preferably no larger than the minimum photolithography spacing limits. Single sidewall oxide spacers (24) are formed on the sidewalls of the nitride mask by depositing a conformal coating of oxide and then applying an anisotropic etch, leaving the oxide spacers (24) of approximately 100 to 500 Angstroms thickness on the sidewalls of the nitride mask (16). Isolation trenches (26) are etched into a silicon substrate (12) in the spaces between adjacent ones of the oxide spacers (24). The oxide spacers (24) are then removed without removing the nitride mask (16), leaving ledges, or shelf regions (28), of the substrate (12) in the spaces between the trenches (26) and the nitride mask (16). Channel stops (30) are implanted into the shelf regions (28). Oxide plugs (34) are formed within the trenches (26). Double sidewall spacers, such as nitride spacers (114) and oxide spacers (118), may be used to reduce the width of the trench isolation structure (140). The edges (66) of the isolation trench (60) may also be rounded.

摘要翻译： 公开了一种用于制造集成电路的结构和方法，其中在集成电路（10）的有源区（38）之间形成窄沟槽隔离结构（36）。 沉积，图案化和蚀刻氮化硅层以提供具有优选不大于最小光刻间隔极限的空间（20）的氮化物掩模（16）。 通过沉积氧化物的保形涂层，然后施加各向异性蚀刻，在氮化物掩模的侧壁上形成单个侧壁氧化物间隔物（24），使得氧化物间隔物（24）在氮化物的侧壁上留下大约100至500埃的厚度 面具（16）。 绝缘沟槽（26）被蚀刻到相邻的氧化物间隔物（24）之间的空间中的硅衬底（12）中。 然后去除氧化物间隔物（24），而不去除在沟槽（26）和氮化物掩模（16）之间的空间中的衬底（12）的氮化物掩模（16），留下栅极或搁板区域（28） 。 通道停止（30）被植入搁板区域（28）。 氧化物塞（34）形成在沟槽（26）内。 可以使用诸如氮化物间隔物（114）和氧化物间隔物（118）的双侧壁间隔物来减小沟槽隔离结构（140）的宽度。 隔离沟槽（60）的边缘（66）也可以是圆形的。

公开(公告)号：US5917212A

公开(公告)日：1999-06-29

申请号：US434257

申请日：1995-05-03

申请人： Terence G. W. Blake ,  Theodore W. Houston

发明人： Terence G. W. Blake ,  Theodore W. Houston

IPC分类号： G11C5/00 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/108

CPC分类号： G11C5/005 ,  G11C11/4125 ,  H01L27/1104 ,  Y10S257/904

摘要： A compact capacitor for use in a small memory cell in high density memories is disclosed. Such a capacitor in the cross-coupling of cross-coupled inverters in the memory cell improves single event upset hardness. The subject capacitor in its preferred embodiment is a MOS capacitor with both n+ and p+ connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages.

摘要翻译： 公开了一种用于高密度存储器中的小存储单元的小型电容器。 交叉耦合逆变器在存储单元中的交叉耦合中的这种电容器改善了单事件镦粗硬度。 在其优选实施例中的目标电容器是具有与电容器通道的n +和p +连接的MOS电容器，以便为正和负电容器栅极电压保持相对较高的电容。

公开(公告)号：US5905290A

公开(公告)日：1999-05-18

申请号：US101348

申请日：1993-08-02

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： G11C11/41 ,  G11C11/412 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L29/76

CPC分类号： G11C11/4125

摘要： A bi-stable logic device 110 comprises first and second inverters 112 and 114. A first resistive connection 140 is made between the input 134 of the first inverter 112 and the output B.sub.-- of the second inverter 114 and a second resistive connection 142 is made between the input 138 of the second inverter 114 and the output B of the first inverter 112. The first and said second resistive connections are also capacitively coupling. The device 110 is hardened from single event upset. Other systems and methods are also disclosed.

摘要翻译： 双稳态逻辑器件110包括第一和第二反相器112和114.在第一反相器112的输入134与第二反相器114的输出B-之间形成第一电阻连接140，并且制成第二电阻连接142 在第二反相器114的输入端138与第一反相器112的输出端B之间。第一和第二电阻连接也是电容耦合的。 装置110从单一事件的不适中硬化。 还公开了其它系统和方法。

公开(公告)号：US5600274A

公开(公告)日：1997-02-04

申请号：US993502

申请日：1992-12-17

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： H03K5/13 ,  H03K5/1534 ,  H03H11/26 ,  H03K3/00 ,  H03K5/02 ,  H03K17/14

CPC分类号： H03K5/1534

摘要： A compensation circuit 10 is disclosed herein. The circuit includes a control circuit 14 including a delay element 18 with a delay sensitive to at least one parameter which causes variations in delay and also comprises a compensated driver circuit 16. The compensated driver circuit 16 has a control input B coupled to the control circuit 14 and a signal input C coupled to an input circuit 12. The delay of an output signal OUT of the compensated driver circuit 16 is controlled in part by the control circuit 14 which modifies the delay of the output signal OUT in response to variation of the parameter. Other systems and methods and numerous variations are also disclosed.

摘要翻译： 这里公开了补偿电路10。 该电路包括一个控制电路14，该延迟元件18具有对至少一个引起延迟变化的参数的延迟敏感的延迟元件18，并且还包括经补偿的驱动电路16.经补偿的驱动电路16具有耦合到控制电路 14和耦合到输入电路12的信号输入C。补偿的驱动器电路16的输出信号OUT的延迟部分由控制电路14控制，控制电路14响应于输入信号OUT的变化来修改输出信号OUT的延迟 参数。 还公开了其它系统和方法以及许多变化。

公开(公告)号：US5541882A

公开(公告)日：1996-07-30

申请号：US369951

申请日：1995-01-09

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： G11C8/06 ,  G11C8/20 ,  G11C7/00

CPC分类号： G11C8/20 ,  G11C8/06

摘要： A delay circuit (10) for a memory device introduces asymmetrical delay to prevent a false write operation from being performed by the memory device, The asymmetrical delay can be disabled during read operations in response to a control signal (CS) in order to allow for fast column access.

摘要翻译： 用于存储器件的延迟电路（10）引入不对称延迟以防止存储器件执行错误写入操作。响应于控制信号（CS），在读取操作期间可以禁用不对称延迟，以便允许 快速列访问。

公开(公告)号：US5436173A

公开(公告)日：1995-07-25

申请号：US753

申请日：1993-01-04

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/265

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  Y10S148/012 ,  Y10S148/05 ,  Y10S148/135

摘要： A method for forming a semiconductor on insulator device is provided that begins with an outer semiconductor layer (16). Trenches (12) of a predetermined depth are formed in outer semiconductor layer (16). An insulator layer (20) is formed outwardly from outer semiconductor layer (16). A mesa (18a) having a predetermined thickness is formed by removing portions of outer semiconductor layer (16) to expose a working surface such that mesa (18a) has a thickness substantially equal to the predetermined depth of the trenches (12) after the working surface is exposed.

摘要翻译： 提供一种用于形成绝缘体上半导体器件的方法，其以外部半导体层（16）开始。 在外半导体层（16）中形成预定深度的沟槽（12）。 绝缘体层（20）从外部半导体层（16）向外形成。 通过去除外部半导体层（16）的部分以暴露工作表面，使得台面（18a）具有基本上等于工作后的沟槽（12）的预定深度的厚度，形成具有预定厚度的台面（18a） 表面露出。

公开(公告)号：US5422852A

公开(公告)日：1995-06-06

申请号：US300574

申请日：1994-09-02

申请人： Theodore W. Houston ,  Larry R. Hite ,  Robert A. Bell

发明人： Theodore W. Houston ,  Larry R. Hite ,  Robert A. Bell

IPC分类号： G11C29/50 ,  G01R31/30 ,  G06F11/00 ,  G11C7/00

CPC分类号： G11C29/028 ,  G11C29/50 ,  G11C29/50016 ,  G11C11/41 ,  G11C2029/5004

摘要： A method of testing a circuit having one or more memory cells, such as a random access memory, register or latch, is disclosed herein. A selected pattern (e.g., all "1"s, all "0"s, or alternating "1"s and "0 38 s) is stored (block 10) in each memory cell of the circuit under test. The power to-each of the cells is then lowered (block 12) to a selected voltage level which is below the static holding voltage, but greater than zero volts. The voltage level may have been previously determined. After a selected time period (which may also have been previously determined), the power to each of the cells is restored (block 14) and the logical state present in each cell is compared (block 16) with the initially stored logical state to determine if any of the cells have switched to another logical state. This procedure may be repeated (blocks 18-26) a number of times. Other systems and methods are also disclosed.

摘要翻译： 本文公开了一种测试具有一个或多个存储器单元（例如随机存取存储器，寄存器或锁存器）的电路的方法。 在被测电路的每个存储单元中存储所选择的模式（例如，所有“1”，全“0”或交替“1”和“038s）（框10） 然后每个单元被降低（块12）到低于静态保持电压但大于零伏特的选定电压电平，可以预先确定电压电平，在选定的时间段（也可能已经 先前确定），恢复对每个小区的功率（框14），并且将存在于每个小区中的逻辑状态与初始存储的逻辑状态进行比较（方框16），以确定是否有任何小区切换到另一个逻辑状态 该过程可以重复（框18-26）多次，还公开了其他系统和方法。