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    System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups
    41.
    发明授权
    System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups 失效
    用于异步DMA命令完成通知的系统，其中包括标签的DMA命令属于多个标签组

    公开(公告)号：US07546393B2

    公开(公告)日：2009-06-09

    申请号：US11695436

    申请日：2007-04-02

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.

    摘要翻译： 本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。 计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。 标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。 并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

    System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB Bus
    44.
    发明申请
    System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB Bus 审中-公开
    通过BEB总线通过仅数据传输协议向Getllar命中缓存行数据转发的系统和方法

    公开(公告)号：US20090077322A1

    公开(公告)日：2009-03-19

    申请号：US11857674

    申请日：2007-09-19

    申请人： Charles Ray Johns ,  Roy Moonseuk Kim ,  Peichun Peter Liu ,  Shigehiro Asano ,  Anushkumar Rengarajan

    发明人： Charles Ray Johns ,  Roy Moonseuk Kim ,  Peichun Peter Liu ,  Shigehiro Asano ,  Anushkumar Rengarajan

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831 ,  G06F2212/1016

    摘要： A system and method for using a data-only transfer protocol to store atomic cache line data in a local storage area is presented. A processing engine includes an atomic cache and a local storage. When the processing engine encounters a request to transfer cache line data from the atomic cache to the local storage (e.g., GETTLAR command), the processing engine utilizes a data-only transfer protocol to pass cache line data through the external bus node and back to the processing engine. The data-only transfer protocol comprises a data phase and does not include a prior command phase or snoop phase due to the fact that the processing engine communicates to the bus node instead of an entire computer system when the processing engine sends a data request to transfer data to itself.

    摘要翻译： 提出了一种使用仅数据传输协议将原始高速缓存行数据存储在本地存储区域中的系统和方法。 处理引擎包括原子缓存和本地存储。 当处理引擎遇到将高速缓存行数据从原子缓存传送到本地存储器（例如，GETTLAR命令）的请求时，处理引擎利用仅数据传输协议通过外部总线节点传递高速缓存行数据并返回 处理引擎。 仅数据传输协议包括数据相位，并且不包括先前的命令阶段或窥探阶段，因为当处理引擎发送数据请求传送时处理引擎与总线节点而不是整个计算机系统通信 数据本身。

    Support of deep power savings mode and partial good in a thermal management system
    45.
    发明授权
    Support of deep power savings mode and partial good in a thermal management system 有权
    支持深度节电模式和部分良好的热管理系统

    公开(公告)号：US07460932B2

    公开(公告)日：2008-12-02

    申请号：US11425462

    申请日：2006-06-21

    申请人： Charles Ray Johns ,  Michael Fan Wang

    发明人： Charles Ray Johns ,  Michael Fan Wang

    IPC分类号： G05D5/00 ,  G05D7/00 ,  G05D11/00 ,  G05D23/00

    CPC分类号： G06F1/3203 ,  G01K3/005 ,  G01K7/015 ,  G06F1/206 ,  Y02D10/16

    摘要： A computer implemented method, data processing system, and processor are provided for managing a thermal management system. A determination is made as to whether a plurality of digital thermal sensors is faulty or functional. A power savings mode of at least one unit within the integrated circuit associated with the functional digital thermal sensor is monitored in response to at least one of the plurality of digital thermal sensors being functional. A functional digital thermal sensor is disabled in response to the at least one unit being in a power savings mode.

    摘要翻译： 提供计算机实现的方法，数据处理系统和处理器来管理热管理系统。 确定多个数字热传感器是否有故障或功能。 响应于所述多个数字热传感器中的至少一个正在起作用，来监视与功能数字热传感器相关联的集成电路内的至少一个单元的功率节省模式。 响应于至少一个单元处于省电模式，功能数字热传感器被禁用。

    Method and Apparatus for Power Throttling a Processor in an Information Handling System
    46.
    发明申请
    Method and Apparatus for Power Throttling a Processor in an Information Handling System 有权
    用于在信息处理系统中调节处理器的功率的方法和装置

    公开(公告)号：US20080168287A1

    公开(公告)日：2008-07-10

    申请号：US11621710

    申请日：2007-01-10

    申请人： Robert Walter Berry ,  Charles Ray Johns ,  Christopher J. Kuruts

    发明人： Robert Walter Berry ,  Charles Ray Johns ,  Christopher J. Kuruts

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/266 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3891 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20

    摘要： A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The power system may reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actual output voltage that processor circuitry receives from the power system in comparison to an expected output voltage over time and corrects for such variance.

    摘要翻译： 电力系统耦合到多核处理器以向处理器供电。 当处理器从电力系统消耗的功率超过预定阈值功率时，电力系统节流处理器的至少一个核心。 电力系统可以降低特定核心或时钟门指令发出的速率，以提供功率节流。 与期望的输出电压相比，电力系统动态响应处理器电路从电力系统接收的实际输出电压的变化，并对这种变化进行校正。

    Non-Homogeneous Multi-Processor System With Shared Memory
    47.
    发明申请
    Non-Homogeneous Multi-Processor System With Shared Memory 审中-公开
    具有共享内存的非均匀多处理器系统

    公开(公告)号：US20080162877A1

    公开(公告)日：2008-07-03

    申请号：US12049324

    申请日：2008-03-15

    申请人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

    发明人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： H04L63/168 ,  H04L67/10

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

    System and method for flexible multiple protocols
    48.
    发明授权
    System and method for flexible multiple protocols 有权
    灵活多协议的系统和方法

    公开(公告)号：US07389363B2

    公开(公告)日：2008-06-17

    申请号：US11050022

    申请日：2005-02-03

    申请人： Scott Douglas Clark ,  Charles Ray Johns ,  James Allan Kahle

    发明人： Scott Douglas Clark ,  Charles Ray Johns ,  James Allan Kahle

    IPC分类号： G06F3/00

    CPC分类号： G06F13/385

    摘要： A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.

    摘要翻译： 介绍了灵活多协议的系统和方法。 可以在每个接口的基础上动态地配置设备的逻辑层，以以相干或非相干模式与外部设备进行通信。 在相干模式下，诸如一致性协议，系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备，从而创建设备内部系统总线的逻辑扩展。 在非相干模式下，输入 - 输出总线单元从内部系统总线接收命令，并产生最终由外部设备接收的非相干输入 - 输出命令。