公开(公告)号：US07579271B2

公开(公告)日：2009-08-25

申请号：US11418501

申请日：2006-05-03

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/4763

CPC classification number: H01L21/02131 ,  C23C16/30 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31604 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/7684 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract translation: 提供一种形成半导体器件的方法。 在一个实施例中，该方法包括提供具有表面区域的半导体衬底。 表面区域包括覆盖半导体衬底的一个或多个层。 此外，该方法包括沉积覆盖表面区域的介电层。 介电层通过CVD工艺形成。 此外，该方法包括形成覆盖在电介质层上的扩散阻挡层。 此外，该方法包括形成覆盖扩散阻挡层的导电层。 另外，该方法包括使用化学机械抛光工艺来减小导电层的厚度。 CVD工艺利用氟作为反应物形成电介质层。 此外，介电层与等于或小于3.3的介电常数相关联。

公开(公告)号：US07456067B2

公开(公告)日：2008-11-25

申请号：US11539612

申请日：2006-10-06

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/44 ,  H01L21/00

CPC classification number: H01L21/76224

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract translation: 提供了一种用于半导体器件的STI间隙填充处理的方法。 在本发明的具体实施方案中，该方法包括形成覆盖衬底的阻挡层。 此外，该方法包括在衬底内形成沟槽，其中沟槽具有侧壁，底部和深度。 该方法还包括在沟槽内形成衬垫，衬垫衬在沟槽的侧壁和底部。 此外，该方法包括用第一氧化物将沟槽填充到第一深度。 使用旋涂工艺填充第一氧化物。 该方法还包括对沟槽内的第一氧化物进行第一致密化处理。 另外，该方法包括使用HDP工艺在沟槽内沉积第二氧化物以填充至少整个沟槽。 该方法还包括对沟槽内的第一和第二氧化物进行第二致密化处理。

公开(公告)号：US06787422B2

公开(公告)日：2004-09-07

申请号：US09755572

申请日：2001-01-08

Applicant: Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

Inventor： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/78615

Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

Abstract translation: 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

公开(公告)号：US06653674B2

公开(公告)日：2003-11-25

申请号：US10227124

申请日：2002-08-23

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

IPC: H01L2976

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/78621

Abstract: A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant implantation is in the exposed the source/drain junctions. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

公开(公告)号：US06495399B1

公开(公告)日：2002-12-17

申请号：US09431238

申请日：1999-11-01

Applicant: Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

Inventor： Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

IPC: H01L2150

CPC classification number: H01L23/3107 ,  H01L23/5221 ,  H01L23/5222 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.

Abstract translation: 一种半导体芯片器件封装，包括形成在半导体衬底上的具有半导体器件的半导体衬底。 至少一个电介质层在半导体衬底之上。 至少一层互连在半导体器件之上，并且在至少一个相应的电介质层内，其中至少一部分互连由其中具有真空或空气的空隙分开。 钝化层位于至少一层互连层的最上面。 其中半导体芯片器件被真空密封在半导体芯片器件封装内。

公开(公告)号：US06455384B2

公开(公告)日：2002-09-24

申请号：US09972645

申请日：2001-10-09

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

Abstract translation: 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

公开(公告)号：US06416909B1

公开(公告)日：2002-07-09

申请号：US09618673

申请日：2000-07-18

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Swee Hong Choo ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Swee Hong Choo ,  Sang Yee Loong

IPC: G03F900

CPC classification number: G03F1/30 ,  G03F7/70216

Abstract: A new process for fabricating an alternating phase-shifting photomask having an alignment monitor is described. An opaque layer is provided overlying a substrate. The opaque layer is patterned to provide a mask pattern. A phase-shifting pattern is formed on the substrate wherein a portion of the phase-shifting pattern comprises an alignment monitor whereby alignment between the mask pattern and the phase-shifting pattern can be tested.

Abstract translation: 描述了一种用于制造具有对准监视器的交替移相光掩模的新工艺。 覆盖在衬底上的不透明层被提供。 将不透明层图案化以提供掩模图案。 在基板上形成有一个移相图案，其中一部分移相图案包括对准监视器，从而可以测试掩模图案和移相图案之间的对准。

公开(公告)号：US06329253B1

公开(公告)日：2001-12-11

申请号：US09434922

申请日：1999-11-05

Applicant: Jun Song ,  Yonqzang Zhang ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Cai ,  Puay Ing Ong

Inventor： Jun Song ,  Yonqzang Zhang ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Cai ,  Puay Ing Ong

IPC: H01L21336

CPC classification number: H01L29/66621 ,  H01L21/76224 ,  H01L27/0266 ,  H01L29/7834

Abstract: A method for forming a novel thick oxide electrostatic discharge device using shallow trench isolation technology is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. The oxide within the trench is partially etched away leaving the oxide on the sidewalls and bottom of the trench. The oxide is polished away to the surface of the semiconductor substrate whereby oxide remains only on the sidewalls and bottom of the trench. A gate is formed within the trench whereby the gate is surrounded by the oxide. First ions are implanted into the semiconductor substrate adjacent to the trench to form N-wells. Second ions are implanted into the semiconductor substrate in a top portion of the N-wells to form source/drain regions. Third ions are implanted into the semiconductor substrate underlying the N-wells and underlying the trench to form electrostatic discharge trigger taps. This completes formation of an electrostatic discharge device in the fabrication of integrated circuits.

Abstract translation: 描述了使用浅沟槽隔离技术形成新的厚氧化物静电放电装置的方法。 将沟槽蚀刻到半导体衬底中。 沉积在半导体衬底上并填充沟槽的氧化物层。 部分地蚀刻沟槽内的氧化物，留下沟槽的侧壁和底部上的氧化物。 氧化物被抛光到半导体衬底的表面，由此氧化物仅保留在沟槽的侧壁和底部上。 在沟槽内形成栅极，由此栅极被氧化物包围。 将第一离子注入到与沟槽相邻的半导体衬底中以形成N阱。 在N阱的顶部将第二离子注入到半导体衬底中以形成源/漏区。 将第三离子注入位于N阱下方并位于沟槽下方的半导体衬底中以形成静电放电触发抽头。 这就形成了集成电路制造中的静电放电装置。

公开(公告)号：US06303414B1

公开(公告)日：2001-10-16

申请号：US09614558

申请日：2000-07-12

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC: H01L2100

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

Abstract translation: 在绝缘体上硅（SOI）型衬底上制造的集成微电子半导体电路可以通过散热，保护等离子体诱导损伤（PID）二极管在制造期间免受不必要的电流浪涌和过度积累热量。 本发明制造这样的保护二极管作为其中形成晶体管器件的整体方案的一部分。

公开(公告)号：US06252290B1

公开(公告)日：2001-06-26

申请号：US09425903

申请日：1999-10-25

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan ,  Sang Yee Loong

IPC: H01L2900

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L2221/1026

Abstract: A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack. The above steps are repeated n-1 times to form n-1 more dual damascene interconnects over the first level dual damascene interconnect where n is the number of interconnect levels desired. A passivation layer is deposited and patterned over the nth metal dual damascene interconnect layer to form openings in the passivation layer. The n number of via photo sensitive dielectric and trench photo sensitive dielectric layers are stripped and removed beneath the passivation layer openings and between the plurality of dual damascene structures wherein the portion of the via photo sensitive dielectric underneath the horizontal metal lines of the stripped trench photo sensitive dielectric layers remains.

Abstract translation: 一种在半导体器件中制造双镶嵌互连结构的方法，包括以下步骤。 通过光敏电介质层的第一级沉积并暴露在半导体结构上。 第一级沟槽光电介质层被沉积并暴露在第一通孔光敏介电层上。 通过光敏电介质和沟槽光敏电介质层曝光的第一级被图案化和蚀刻以形成第一级双镶嵌开口。 第一级双镶嵌开口包括集成的第一级通孔和金属线开口。 第一级金属层沉积在第一级沟槽光敏介电层上，填充第一级双镶嵌开口。 第一级金属层被平坦化以形成具有第一级水平金属线和第一级垂直通孔叠层的至少一个第一级双镶嵌互连。 上述步骤重复n-1次，以在第一级双镶嵌互连上形成n-1个双镶嵌互连，其中n是所需的互连级数。 在第n个金属双镶嵌互连层上沉积并图案化钝化层，以在钝化层中形成开口。 在钝化层开口之下和多个双镶嵌结构之间剥离并除去n个通孔光敏电介质层和沟槽光敏介电层，其中通过光敏电介质的部分在剥离的沟槽照片的水平金属线下方 保持敏感的电介质层。