公开(公告)号：US06297098B1

公开(公告)日：2001-10-02

申请号：US09431236

申请日：1999-11-01

申请人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

发明人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/26586

摘要： A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

摘要翻译： 公开了一种用于在闪速存储器应用中用于非易失性存储器和DDD（双掺杂漏极）的高压器件中形成LDD（轻掺杂漏极）的方法。 高压器件通过以倾斜角度使用两个连续的离子注入形成，其提供了接合点附近的掺杂分布的改进的灰度级，并且在更高的电压下提高了结点击穿。 层叠闪存单元中的双掺杂漏极也通过两次注入形成，但是以最佳倾角形成，其中第一次注入被轻掺杂，而第二次重掺杂。 由此产生的DDD提供更快的编程速度，减少编程电流，增加读取电流和减少闪存单元中的漏极干扰。

公开(公告)号：US6153494A

公开(公告)日：2000-11-28

申请号：US310257

申请日：1999-05-12

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

摘要翻译： 提供一种用于形成具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极快闪存储器单元的方法。 这是通过首先沉积非常规高或较厚的氮化物层，然后通过氮化物层形成浅沟槽隔离（STI）到衬底中，用隔离氧化物填充STI，从而除去氮化物，从而留下围绕 填充STI，用第一多晶硅层保形地填充开口以形成浮置栅极，在浮置栅极上形成多晶硅层，然后形成第二多晶硅层以形成控制栅极，并最终形成堆叠的自对准源 本发明的闪存单元。 还提供了堆叠栅极闪存单元，其具有具有高阶氧化物和高横向耦合的浅沟槽隔离。

公开(公告)号：US6037223A

公开(公告)日：2000-03-14

申请号：US177342

申请日：1998-10-23

申请人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Di-Son Kuo

发明人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： A process for fabricating a flash memory cell, featuring self-aligned contact structures, overlying and contacting, self-aligned source, and self-aligned drain regions, located between stack gate structures, has been developed. The stack gate structures, located on an underlying silicon dioxide, tunnel oxide layer, are comprised of: a capping insulator shape; a polysilicon control gate shape; an inter-polysilicon dielectric shape; and a polysilicon floating gate shape. The use of self-aligned contact structures, and self-aligned source regions, allows increased cell densities to be achieved.

摘要翻译： 已经开发了一种用于制造闪存单元的方法，其特征在于位于堆叠栅极结构之间的自对准接触结构，覆盖和接触自对准源极和自对准漏极区。 位于下面的二氧化硅隧道氧化物层上的堆叠栅极结构包括：封盖绝缘体形状; 多晶硅控制门形状; 多晶硅间介质形状; 和多晶硅浮栅形状。 使用自对准接触结构和自对准的源区域可以实现提高的细胞密度。

公开(公告)号：US6001687A

公开(公告)日：1999-12-14

申请号：US283849

申请日：1999-04-01

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/8239

CPC分类号： H01L27/11521

摘要： When FLASH cells are made in association with STI (as opposed to LOCOS) it is often the case that stringers of silicon nitride are left behind after the spacers have been formed. This problem has been eliminated by requiring that the oxide in the STI trenches remain in place at the time that the silicon nitride spacers are formed. After that, the oxide is removed in the usual manner, following which a SALICIDE process is used to form a self aligned source line. When this sequence is followed no stringers are left behind on the walls of the trench, guaranteeing the absence of any open circuits or high resistance regions in the source line.

摘要翻译： 当与STI（与LOCOS相反）制成FLASH单元时，通常在形成间隔物之后留下氮化硅桁条。 通过要求在形成氮化硅间隔物的时刻STI槽中的氧化物保持在适当位置，已经消除了这个问题。 之后，以通常的方式去除氧化物，随后使用SALICIDE工艺来形成自对准的源极线。 当遵循该顺序时，沟槽的壁上不留下桁条，保证在源极线中不存在任何开路或高电阻区域。

公开(公告)号：US20180306742A1

公开(公告)日：2018-10-25

申请号：US15495136

申请日：2017-04-24

申请人： Yu-Lin Yang ,  Chun-Hao Chang ,  Min-Da Wu ,  Hung-Der Su ,  Da-Hong Qian

发明人： Yu-Lin Yang ,  Chun-Hao Chang ,  Min-Da Wu ,  Hung-Der Su ,  Da-Hong Qian

IPC分类号： G01N27/22 ,  B01L3/00

CPC分类号： G01N27/22 ,  B01L3/502 ,  B01L3/508 ,  B01L2200/12 ,  B01L2300/0627 ,  B01L2300/0645 ,  B01L2300/0663 ,  B01L2300/0887 ,  B01L2300/161 ,  G01N27/226

摘要： The invention provides a bio-detection device, including a carrier, a plurality of spacers, an electronic circuit, and a package layer, wherein an open platform is formed. The carrier includes a test region and a signal transmission wiring, wherein the test region is configured to carry a fluid under test. The spacers are located on the test region and electrically connected to two different voltage levels to form a capacitor for sensing a capacitance of the fluid. The spacers are connected to the signal transmission wiring. The electronic circuit receives and processes a sensing signal corresponding to the capacitance of the fluid. The package layer covers a portion of the carrier but does not cover the test region. The open platform is formed whereby a user can easily put in the fluid. The open platform has a bottom which includes the test region, and an area of the open platform is defined by the spacers and the package layer.

公开(公告)号：US20160155820A1

公开(公告)日：2016-06-02

申请号：US15018672

申请日：2016-02-08

申请人： Tsung-Yi Huang ,  Ching-Yao Yang ,  Wen-Yi Liao ,  Hung-Der Su ,  Kuo-Cheng Chang

发明人： Tsung-Yi Huang ,  Ching-Yao Yang ,  Wen-Yi Liao ,  Hung-Der Su ,  Kuo-Cheng Chang

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/66681 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/6681 ,  H01L29/7816

摘要： The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.

公开(公告)号：US20140159111A1

公开(公告)日：2014-06-12

申请号：US14048971

申请日：2013-10-08

申请人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

发明人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

IPC分类号： H01L21/02 ,  H01L29/12

CPC分类号： H01L29/205 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/30612 ,  H01L29/12 ,  H01L29/2003 ,  H01L29/7845 ,  H01L29/7849

摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.

摘要翻译： 本发明公开了一种具有异质结的半导体复合膜及其制造方法。 半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步 包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。 该凹槽用于减轻半导体复合膜中的应变。

公开(公告)号：US20120181653A1

公开(公告)日：2012-07-19

申请号：US13005754

申请日：2011-01-13

申请人： TSUNG-YI HUANG ,  Hung-Der Su ,  Kuo-Cheng Chang ,  Chun-Yi Hung ,  Kuo-Hsuan Lo ,  Jeng Gong

发明人： TSUNG-YI HUANG ,  Hung-Der Su ,  Kuo-Cheng Chang ,  Chun-Yi Hung ,  Kuo-Hsuan Lo ,  Jeng Gong

IPC分类号： H01L29/06 ,  H01L21/04

CPC分类号： H01L29/0688 ,  H01L29/0634 ,  H01L29/0692

摘要： The present invention discloses a semiconductor PN junction structure and a manufacturing method thereof. From top view, the PN junction includes a staggered comb-teeth structure. The PN junction forms a depletion region with enhanced breakdown voltage, hence broadening the applications of a semiconductor device having such PN junction.

摘要翻译： 本发明公开了一种半导体PN结结构及其制造方法。 从顶视图，PN结包括交错的梳齿结构。 PN结形成具有增强的击穿电压的耗尽区，因此拓宽了具有这种PN结的半导体器件的应用。

公开(公告)号：US07839197B2

公开(公告)日：2010-11-23

申请号：US12230953

申请日：2008-09-09

申请人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

发明人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

IPC分类号： H03L5/00

CPC分类号： H03K3/012 ,  H03K3/35613

摘要： A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.

摘要翻译： 电平移位电路包括由两个节点彼此耦合的输入级和输出级。 输入级根据输入信号改变节点上的电压，输出级根据两个节点上的电压来确定输出信号。 在过渡状态下，输入级提供大电流以对第一节点或第二节点进行充电或放电，以便快速地改变其上的电压。 在稳定状态下，输入级降低电流，从而降低功耗。

公开(公告)号：US07838901B2

公开(公告)日：2010-11-23

申请号：US12385719

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.