公开(公告)号：US20100129962A1

公开(公告)日：2010-05-27

申请号：US12693712

申请日：2010-01-26

Applicant: YU-LIN YANG

Inventor： YU-LIN YANG

IPC: H01L21/60

CPC classification number: H01L23/49575 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/37599 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  Y10S257/923 ,  H01L2924/00 ,  H01L2224/37099

Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

Abstract translation: 电子封装结构和方法使用导电条来将芯片到管芯，管芯到引线，芯片载体与引线或引线对引线接合。 导电带可以承载比接合线更大的电流，并且因此可以代替多个接合线。 导电带的接合可以通过SMT工艺进行，因此比引线键合工艺要低。 导电条可以结合到多于两个的骰子或导线上以节省更多的接合线。 导电条比接合线更强，从而降低破损的可能性。

公开(公告)号：US20100124801A1

公开(公告)日：2010-05-20

申请号：US12693719

申请日：2010-01-26

Applicant: YU-LIN YANG

Inventor： YU-LIN YANG

IPC: H01L21/60

CPC classification number: H01L23/49575 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/37599 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  Y10S257/923 ,  H01L2924/00 ,  H01L2224/37099

Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

公开(公告)号：US07528495B2

公开(公告)日：2009-05-05

申请号：US11550304

申请日：2006-10-17

Applicant: Yu-Lin Yang

Inventor： Yu-Lin Yang

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/136 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A chip structure including a substrate, at least one chip bonding pad, a passivation layer, at least one compliant bump, and at least one redistribution conductive trace is provided. The substrate has an active surface whereon the chip bonding pad is disposed. The passivation layer is disposed on the active surface and exposes the chip bonding pad. The compliant bump has a top surface and a side surface. At least part of the compliant bump is disposed on the passivation layer. One end of the redistribution conductive trace is electrically connected to the chip bonding pad and the other end thereof covers part of the side surface and at least part of the top surface of the compliant bump. Therefore, the chip bonding pad of the chip structure can be electrically connected to the corresponding electrical contact of the carrier through the compliant bump and the redistribution conductive trace.

Abstract translation: 提供了一种芯片结构，其包括衬底，至少一个芯片焊盘，钝化层，至少一个顺应性凸块和至少一个再分布导电迹线。 衬底具有其上设置有芯片焊盘的有源表面。 钝化层设置在有源表面上并使芯片接合焊盘露出。 柔性凸块具有顶表面和侧表面。 柔性凸块的至少一部分设置在钝化层上。 再分布导电迹线的一端电连接到芯片接合焊盘，另一端覆盖侧表面的一部分和柔性凸块的顶表面的至少一部分。 因此，芯片结构的芯片焊盘可以通过顺应性凸块和再分布导电迹线电连接到载体的相应电接触。

公开(公告)号：US20080197507A1

公开(公告)日：2008-08-21

申请号：US12068773

申请日：2008-02-12

Applicant: Yu-Lin Yang

Inventor： Yu-Lin Yang

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/49575 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/37599 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  Y10S257/923 ,  H01L2924/00 ,  H01L2224/37099

Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

Abstract translation: 电子封装结构和方法使用导电条来将芯片到管芯，管芯到引线，芯片载体与引线或引线对引线接合。 导电带可以承载比接合线更大的电流，并且因此可以代替多个接合线。 导电带的接合可以通过SMT工艺进行，因此比引线键合工艺要低。 导电条可以结合到多于两个的骰子或导线上以节省更多的接合线。 导电条比接合线更强，从而降低破损的可能性。

公开(公告)号：US20240350564A1

公开(公告)日：2024-10-24

申请号：US18302922

申请日：2023-04-19

Applicant: Yu-Lin Yang

Inventor： Yu-Lin Yang

IPC: A61K35/745 ,  A61K35/747 ,  A61K36/287 ,  A61K36/41 ,  A61K36/42 ,  A61K36/48 ,  A61K36/537 ,  A61K36/605 ,  A61K36/73 ,  A61K36/736 ,  A61P39/00

CPC classification number: A61K35/745 ,  A61K35/747 ,  A61K36/287 ,  A61K36/41 ,  A61K36/42 ,  A61K36/48 ,  A61K36/537 ,  A61K36/605 ,  A61K36/73 ,  A61K36/736 ,  A61P39/00 ,  A61K2035/115

Abstract: A composition with NRF mitochondria activating ingredient has telomere extension, anti-aging and cell-rejuvenating effects, including salvia miltiorrhiza extract, wheat α-amylase inhibitor, and probiotic powder. After taken by users, the composition reaches a health effect by extending the telomere length and to reduce the cell age and get younger.

公开(公告)号：US20100123255A1

公开(公告)日：2010-05-20

申请号：US12693704

申请日：2010-01-26

Applicant: YU-LIN YANG

Inventor： YU-LIN YANG

IPC: H01L23/48

CPC classification number: H01L23/49575 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/37599 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  Y10S257/923 ,  H01L2924/00 ,  H01L2224/37099

Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

公开(公告)号：US20080012150A1

公开(公告)日：2008-01-17

申请号：US11550304

申请日：2006-10-17

Applicant: YU-LIN YANG

Inventor： YU-LIN YANG

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/136 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A chip structure including a substrate, at least one chip bonding pad, a passivation layer, at least one compliant bump, and at least one redistribution conductive trace is provided. The substrate has an active surface whereon the chip bonding pad is disposed. The passivation layer is disposed on the active surface and exposes the chip bonding pad. The compliant bump has a top surface and a side surface. At least part of the compliant bump is disposed on the passivation layer. One end of the redistribution conductive trace is electrically connected to the chip bonding pad and the other end thereof covers part of the side surface and at least part of the top surface of the compliant bump. Therefore, the chip bonding pad of the chip structure can be electrically connected to the corresponding electrical contact of the carrier through the compliant bump and the redistribution conductive trace.

Abstract translation: 提供了包括衬底，至少一个芯片接合焊盘，钝化层，至少一个顺应凸块和至少一个再分布导电迹线的芯片结构。 衬底具有其上设置有芯片焊盘的有源表面。 钝化层设置在有源表面上并使芯片接合焊盘露出。 柔性凸块具有顶表面和侧表面。 柔性凸块的至少一部分设置在钝化层上。 再分布导电迹线的一端电连接到芯片接合焊盘，另一端覆盖侧表面的一部分和柔性凸块的顶表面的至少一部分。 因此，芯片结构的芯片焊盘可以通过顺应性凸块和再分布导电迹线电连接到载体的相应电接触。

公开(公告)号：US20180306742A1

公开(公告)日：2018-10-25

申请号：US15495136

申请日：2017-04-24

Applicant: Yu-Lin Yang ,  Chun-Hao Chang ,  Min-Da Wu ,  Hung-Der Su ,  Da-Hong Qian

Inventor： Yu-Lin Yang ,  Chun-Hao Chang ,  Min-Da Wu ,  Hung-Der Su ,  Da-Hong Qian

IPC: G01N27/22 ,  B01L3/00

CPC classification number: G01N27/22 ,  B01L3/502 ,  B01L3/508 ,  B01L2200/12 ,  B01L2300/0627 ,  B01L2300/0645 ,  B01L2300/0663 ,  B01L2300/0887 ,  B01L2300/161 ,  G01N27/226

Abstract: The invention provides a bio-detection device, including a carrier, a plurality of spacers, an electronic circuit, and a package layer, wherein an open platform is formed. The carrier includes a test region and a signal transmission wiring, wherein the test region is configured to carry a fluid under test. The spacers are located on the test region and electrically connected to two different voltage levels to form a capacitor for sensing a capacitance of the fluid. The spacers are connected to the signal transmission wiring. The electronic circuit receives and processes a sensing signal corresponding to the capacitance of the fluid. The package layer covers a portion of the carrier but does not cover the test region. The open platform is formed whereby a user can easily put in the fluid. The open platform has a bottom which includes the test region, and an area of the open platform is defined by the spacers and the package layer.

公开(公告)号：US08921218B2

公开(公告)日：2014-12-30

申请号：US13475297

申请日：2012-05-18

Applicant: Yu-Lin Yang ,  Tsu-Hsiu Perng ,  Chih Chieh Yeh ,  Li-Shyue Lai

Inventor： Yu-Lin Yang ,  Tsu-Hsiu Perng ,  Chih Chieh Yeh ,  Li-Shyue Lai

IPC: H01L21/283 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845

Abstract: A method and device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.

Abstract translation: 一种包括具有翅片的基板的方法和装置。 在翅片上形成金属栅极结构。 金属栅极结构包括形成在翅片上的应力金属层，使得应力金属层从STI特征延伸到第一高度，第一高度大于翅片高度。 在应力金属层上形成导电金属层。

公开(公告)号：US08659128B2

公开(公告)日：2014-02-25

申请号：US13043782

申请日：2011-03-09

Applicant: Yu-Lin Yang ,  Lih-Ming Doong

Inventor： Yu-Lin Yang ,  Lih-Ming Doong

IPC: H01L23/495

CPC classification number: H01L23/4334 ,  H01L23/49572 ,  H01L2224/16245 ,  H01L2224/73253

Abstract: A flip chip package structure includes a chip placed under a lead frame, a bump on the upper surface of the chip that is electrically connected to the lead of the lead frame, and a backside metal on the lower surface of the chip that is exposed outside an encapsulant encapsulating the chip and a portion of the lead frame.

Abstract translation: 倒装芯片封装结构包括放置在引线框架下面的芯片，芯片上表面上的电连接到引线框架的引线的凸起，以及在外部暴露在芯片的下表面上的背面金属 密封剂封装芯片和引线框架的一部分。