-
公开(公告)号：US08987091B2
公开(公告)日：2015-03-24
申请号：US13976840
申请日：2011-12-23
申请人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
发明人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336 , H01L31/00 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/778 , H01L29/40 , H01L29/20
CPC分类号： H01L29/7787 , H01L21/02241 , H01L21/02252 , H01L21/02255 , H01L21/02258 , H01L21/02458 , H01L21/0254 , H01L21/268 , H01L21/30604 , H01L21/30612 , H01L21/31111 , H01L29/2003 , H01L29/205 , H01L29/365 , H01L29/401 , H01L29/4236 , H01L29/512 , H01L29/518 , H01L29/66462
摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
摘要翻译： 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和III-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。
-
公开(公告)号：US20130292698A1
公开(公告)日：2013-11-07
申请号：US13976840
申请日：2011-12-23
申请人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
发明人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L29/423 , H01L29/40
CPC分类号： H01L29/7787 , H01L21/02241 , H01L21/02252 , H01L21/02255 , H01L21/02258 , H01L21/02458 , H01L21/0254 , H01L21/268 , H01L21/30604 , H01L21/30612 , H01L21/31111 , H01L29/2003 , H01L29/205 , H01L29/365 , H01L29/401 , H01L29/4236 , H01L29/512 , H01L29/518 , H01L29/66462
摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
-
43.发明申请APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE 有权用于改善量子阱器件中并联导通的装置和方法公开(公告)号：US20120326123A1
公开(公告)日：2012-12-27
申请号：US13545358
申请日：2012-07-10
IPC分类号： H01L29/02
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。 可以描述和要求保护其他实施例。
-
44.发明授权Apparatus and methods for improving parallel conduction in a quantum well device 有权用于改善量子阱器件中的并联传导的装置和方法公开(公告)号：US08242001B2
公开(公告)日：2012-08-14
申请号：US13274468
申请日：2011-10-17
IPC分类号： H01L21/20
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。 可以描述和要求保护其他实施例。
-
45.发明申请APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE 审中-公开用于改善量子阱器件中并联导通的装置和方法公开(公告)号：US20130313520A1
公开(公告)日：2013-11-28
申请号：US13956685
申请日：2013-08-01
IPC分类号： H01L29/66
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。 可以描述和要求保护其他实施例。
-
46.发明授权Apparatus and methods for improving parallel conduction in a quantum well device 有权用于改善量子阱器件中的并联传导的装置和方法公开(公告)号：US08080820B2
公开(公告)日：2011-12-20
申请号：US12381832
申请日：2009-03-16
IPC分类号： H01L29/06
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。 可以描述和要求保护其他实施例。
-
公开(公告)号：US08525151B2
公开(公告)日：2013-09-03
申请号：US13545358
申请日：2012-07-10
IPC分类号： H01L29/06
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
-
48.发明申请Apparatus and methods for improving parallel conduction in a quantum well device 有权用于改善量子阱器件中的并联传导的装置和方法公开(公告)号：US20100230658A1
公开(公告)日：2010-09-16
申请号：US12381832
申请日：2009-03-16
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。 可以描述和要求保护其他实施例。
-
公开(公告)号：US09159823B2
公开(公告)日：2015-10-13
申请号：US13977188
申请日：2011-12-09
申请人： Van H. Le , Benjamin Chu-Kung , Harold Hal W. Kennel , Willy Rachmady , Ravi Pillarisetty , Jack T. Kavalieros
发明人： Van H. Le , Benjamin Chu-Kung , Harold Hal W. Kennel , Willy Rachmady , Ravi Pillarisetty , Jack T. Kavalieros
IPC分类号： H01L29/78 , H01L29/66 , H01L29/786 , H01L29/423 , H01L29/06
CPC分类号： H01L29/0673 , H01L21/02532 , H01L21/283 , H01L29/0649 , H01L29/0847 , H01L29/1054 , H01L29/155 , H01L29/161 , H01L29/165 , H01L29/42392 , H01L29/66431 , H01L29/66477 , H01L29/66651 , H01L29/66795 , H01L29/78 , H01L29/7842 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/78681 , H01L29/78687 , H01L29/78696
摘要： Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
摘要翻译： 提供具有包括压缩和拉伸应变外延材料的交替层的沟道区的晶体管结构。 交替的外延层可以在单和多晶体管结构中形成沟道区。 在替代实施例中，两个交替层中的一个被选择性地蚀刻掉以形成剩余材料的纳米带或纳米线。 得到的应变纳米带或纳米线形成晶体管结构的沟道区。 还提供了包括晶体管的计算设备，所述晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区，以及包括包含由应变纳米带或纳米线组成的沟道区的晶体管的计算器件。
-
公开(公告)号：US20130146845A1
公开(公告)日：2013-06-13
申请号：US13758974
申请日：2013-02-04
申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radiosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radiosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L29/775
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译： 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。
-
-
-
-
-
-
-
-
-
搜索结果
102 条记录 (耗时 0.037 秒)
