公开(公告)号：US09722072B2

公开(公告)日：2017-08-01

申请号：US15173728

申请日：2016-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Chia-Min Hung ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.

公开(公告)号：US20170200650A1

公开(公告)日：2017-07-13

申请号：US14993623

申请日：2016-01-12

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/7836

Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

公开(公告)号：US09680010B1

公开(公告)日：2017-06-13

申请号：US15015142

申请日：2016-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Su-Hwa Tsai

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/66613 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.

公开(公告)号：US20170125297A1

公开(公告)日：2017-05-04

申请号：US14925955

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shu-Wen Lin

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/088 ,  H01L21/321 ,  H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/82345 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

公开(公告)号：US20170110536A1

公开(公告)日：2017-04-20

申请号：US14952877

申请日：2015-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/06 ,  G06F17/50 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

公开(公告)号：US20170062444A1

公开(公告)日：2017-03-02

申请号：US14863177

申请日：2015-09-23

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28273 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42336

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

Abstract translation: 提供了包括第一栅极，第二栅极和栅极间电介质层的存储器件。 第一个栅极被埋在基板中。 第二栅极包括金属并且设置在基板上。 栅极间介电层设置在第一和第二栅极之间。 还提供了形成存储器件的方法。

公开(公告)号：US20170025531A1

公开(公告)日：2017-01-26

申请号：US15173728

申请日：2016-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Chia-Min Hung ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.

Abstract translation: 提供了高压金属氧化物半导体（HV MOS）晶体管器件的制造方法。 该制造方法包括以下步骤。 提供半导体衬底。 在半导体衬底上形成有图案的导电结构。 图案化导电结构包括栅极结构和第一子栅极结构。 半导体衬底具有分别设置在栅极结构的两个相对侧上的第一区域和第二区域。 第一子栅极结构设置在半导体衬底的第一区域上。 第一子栅极结构与栅极结构分离。 漏极区域形成在半导体衬底的第一区域中。 在漏极区域和第一子栅极结构上形成第一接触结构。 漏极区域经由第一接触结构电连接到第一子栅极结构。

公开(公告)号：US20160358919A1

公开(公告)日：2016-12-08

申请号：US14727875

申请日：2015-06-02

Applicant: United Microelectronics Corp.

Inventor： Kuan-Chuan Chen ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shih-Yin Hsiao

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/0653 ,  H01L21/28238 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66613

Abstract: A method for forming a high voltage transistor is provided. First, a substrate having a top surface is provided, following by forming a thermal oxide layer on the substrate. At least a part of the thermal oxidation layer is removed to form a recess in the substrate, wherein a bottom surface of the recess is lower than the top surface of the substrate. A gate oxide layer is formed in the recess, then a gate structure is formed on the gate oxide layer. The method further includes forming a source/drain region in the substrate.

Abstract translation: 提供一种用于形成高压晶体管的方法。 首先，提供具有顶面的基板，接着在基板上形成热氧化层。 去除热氧化层的至少一部分以在衬底中形成凹部，其中凹部的底表面低于衬底的顶表面。 在凹部中形成栅极氧化层，然后在栅极氧化物层上形成栅极结构。 该方法还包括在衬底中形成源极/漏极区域。

公开(公告)号：US09461133B1

公开(公告)日：2016-10-04

申请号：US14748255

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kun-Huang Yu

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L29/66 ,  H01L21/266 ,  H01L29/10

CPC classification number: H01L29/4238 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28105 ,  H01L21/28114 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage metal-oxide-semiconductor transistor device having stepped gate structure and a manufacturing method thereof are provided. The manufacturing method includes following steps. A gate structure is formed on a semiconductor substrate. The semiconductor substrate includes a first region and a second region disposed on a side of a first part of the gate structure and a side of a second part of the gate structure respectively. A patterned mask layer is formed on the semiconductor substrate and the gate structure. The patterned mask layer covers the first region and the first part. The second part is uncovered by the patterned mask layer. An implantation process is performed to form a drift region in the second region. An etching process is performed to remove a part of the second part uncovered by the patterned mask layer. A thickness of the second part is less than that of the first part after the etching process.

Abstract translation: 本发明提供一种具有台阶门结构的高电压金属氧化物半导体晶体管器件及其制造方法。 制造方法包括以下步骤。 栅极结构形成在半导体衬底上。 半导体衬底包括分别设置在栅极结构的第一部分的侧面上的第一区域和第二区域以及栅极结构的第二部分的一侧。 在半导体衬底和栅极结构上形成图案化掩模层。 图案化掩模层覆盖第一区域和第一部分。 第二部分被图案化掩模层覆盖。 执行注入处理以在第二区域中形成漂移区域。 执行蚀刻处理以去除未被图案化掩模层覆盖的第二部分的一部分。 在蚀刻处理之后，第二部分的厚度小于第一部分的厚度。

公开(公告)号：US20160141359A1

公开(公告)日：2016-05-19

申请号：US14542672

申请日：2014-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chung Yang ,  Shih-Yin Hsiao

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/7621 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a silicon oxide layer disposed on the substrate, and at least part of a gate electrode covering the silicon oxide layer. A top surface of the silicon oxide layer is in the shape of plural hills. The silicon oxide layer can provide low on-state resistance for the semiconductor structure.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，设置在衬底上的氧化硅层和覆盖氧化硅层的栅电极的至少一部分。 氧化硅层的上表面为多个山丘的形状。 氧化硅层可以为半导体结构提供低导通电阻。