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    Processing of cacheable streaming data
    45.
    发明申请
    Processing of cacheable streaming data 审中-公开
    可缓存流数据的处理

    公开(公告)号：US20070150653A1

    公开(公告)日：2007-06-28

    申请号：US11315853

    申请日：2005-12-22

    Applicant: Niranjan Cooray ,  Jack Doweck ,  Mark Buxton ,  Varghese George

    Inventor： Niranjan Cooray ,  Jack Doweck ,  Mark Buxton ,  Varghese George

    IPC: G06F12/00

    CPC classification number: G06F12/0888 ,  G06F12/0831 ,  G06F12/0859

    Abstract: According to one embodiment of the invention, a method is disclosed for receiving a request for cacheable memory type data in a cache-controller in communication with a first cache memory; obtaining the requested data from a first memory device in communication with the first cache memory if the requested data does not resides in at least one of the cache-controller and the first cache memory; allocating a data storage buffer in the cache-controller for storage of the obtained data; and setting the allocated data storage buffer to a streaming data mode if the obtained data is a streaming data to prevent an unrestricted placement of the obtained streaming data into the first cache memory.

    Abstract translation: 根据本发明的一个实施例，公开了一种用于在与第一高速缓存存储器通信的高速缓存控制器中接收对可缓存存储器类型数据的请求的方法; 如果所请求的数据不驻留在所述高速缓存控制器和所述第一高速缓冲存储器中的至少一个中，则从与所述第一高速缓存存储器通信的第一存储器设备获得所请求的数据; 在所述高速缓存控制器中分配数据存储缓冲器以存储所获得的数据; 以及如果所获得的数据是流数据，则将所分配的数据存储缓冲器设置为流数据模式，以防止所获得的流数据被无限制地放置到第一高速缓冲存储器中。

    Maintaining processor execution during frequency transitioning
    46.
    发明授权
    Maintaining processor execution during frequency transitioning 有权
    在频率转换期间维护处理器执行

    公开(公告)号：US07210054B2

    公开(公告)日：2007-04-24

    申请号：US10180836

    申请日：2002-06-25

    Applicant: Sanjeev Jahagirdar ,  Islam Derhalli ,  Varghese George ,  Kedar Mangrulkar ,  Mathew Nazareth

    Inventor： Sanjeev Jahagirdar ,  Islam Derhalli ,  Varghese George ,  Kedar Mangrulkar ,  Mathew Nazareth

    IPC: G06F1/04

    CPC classification number: G06F1/08

    Abstract: An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is generated by a core clock generator during a normal operation mode. The core clock generator stops the core clock during a frequency transition. The selector generates a processor clock from the standby clock during the frequency transition from the normal operation mode according to a selector control signal.

    Abstract translation: 本发明的实施例包括备用时钟发生器和选择器。 备用时钟发生器产生与内核时钟同步的备用时钟。 内核时钟由正常操作模式下的核心时钟发生器产生。 核心时钟发生器在频率转换期间停止核心时钟。 根据选择器控制信号，从正常操作模式的频率转换期间，选择器从待机时钟产生处理器时钟。

    Self-programmable bidirectional buffer circuit and method
    47.
    发明授权
    Self-programmable bidirectional buffer circuit and method 有权
    自编程双向缓冲电路及方法

    公开(公告)号：US07205793B2

    公开(公告)日：2007-04-17

    申请号：US11393934

    申请日：2006-03-30

    Applicant: Varghese George

    Inventor： Varghese George

    IPC: H03K19/0175

    CPC classification number: H03K19/01759

    Abstract: The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes. The method includes applying a configuration signal on one of the first and second signal nodes and configuring the buffer responsive to the applied configuration signal.

    Abstract translation: 本发明涉及用于编程这种缓冲器的可编程双向缓冲器和方法。 根据本发明的一个方面的一种方法是配置包括第一和第二信号节点的双向缓冲器的方法。 该方法包括在第一和第二信号节点之一上应用配置信号并且响应于所应用的配置信号来配置缓冲器。

    On-die real time leakage energy meter
    49.
    发明申请
    On-die real time leakage energy meter 审中-公开
    片上实时泄漏电能表

    公开(公告)号：US20070001694A1

    公开(公告)日：2007-01-04

    申请号：US11173147

    申请日：2005-06-30

    Applicant: Sanjeev Jahagirdar ,  Jose Allarey ,  Varghese George

    Inventor： Sanjeev Jahagirdar ,  Jose Allarey ,  Varghese George

    IPC: G01R31/02

    CPC classification number: G01R31/2891 ,  G01R21/02

    Abstract: A method includes measuring a temperature for a portion of an electronic component, determining the voltage being applied to the portion of the component, and determining a leakage power for the component portion based on a measured temperature and determined voltage for the portion of the component. The method also includes measuring a temperature for another portion of the component, determining the voltage being applied to the other component portion, and determining a leakage power for the other component portion based on the measured temperature and determined voltage for the other portion of the component. The method also includes summing the leakage power for the portion with the leakage power for the other portion of the component.

    Abstract translation: 一种方法包括测量电子部件的一部分的温度，确定施加到部件的该部分的电压，并且基于部件的该部分的测量温度和确定的电压来确定部件部分的泄漏功率。 该方法还包括测量部件的另一部分的温度，确定施加到另一部件部分的电压，以及基于所测量的温度和组件的其它部分的确定电压来确定另一部件部分的泄漏功率 。 该方法还包括对具有部件的其他部分的泄漏功率的部分的泄漏功率求和。

    Modular data transfer architecture
    50.
    发明申请
    Modular data transfer architecture 有权
    模块化数据传输架构

    公开(公告)号：US20060123154A1

    公开(公告)日：2006-06-08

    申请号：US11005926

    申请日：2004-12-06

    Applicant: Varghese George

    Inventor： Varghese George

    IPC: G06F13/28

    CPC classification number: G06F15/7825

    Abstract: A system on chip (SoC) integrated circuit includes a plurality of computational blocks. A modular data transfer architecture interconnects the computational blocks for intra-chip communications. The computational blocks include an initiator block and a target block, with the initiator block originating a data communication having a global address associated with the target block. The modular data transfer architecture includes a first peripheral module having an initiator port connected to the initiator block to receive the data communication and a second peripheral module having a target port connected to the target block. A first port mapper within the first peripheral module maps the global address to a first peripheral module target port along a data path towards the second peripheral module. A second port mapper within the second peripheral module maps the global address to the target port connected to the target block. The modular data transfer architecture further includes a plurality of internal modules support intra-chip communications. Each internal module has a plurality of initiator ports connected to target ports of other modules and a plurality of target ports connected to initiator ports of other modules. An internal port mapper for each internal module maps the global address to a certain internal module target port along the data path towards the second peripheral module.

    Abstract translation: 片上系统（SoC）集成电路包括多个计算块。 模块化数据传输架构将用于片内通信的计算块互连。 计算块包括发起者块和目标块，其中发起者块发起具有与目标块相关联的全局地址的数据通信。 模块化数据传输架构包括第一外围模块，其具有连接到启动器块的发起端口以接收数据通信，以及具有连接到目标块的目标端口的第二外围模块。 第一外围模块内的第一端口映射器将全局地址映射到沿第二外围模块的数据路径的第一外围模块目标端口。 第二个外围模块中的第二个端口映射器将全局地址映射到连接到目标块的目标端口。 模块化数据传输架构还包括多个内部模块支持片上通信。 每个内部模块具有连接到其他模块的目标端口的多个启动器端口和连接到其他模块的启动器端口的多个目标端口。 每个内部模块的内部端口映射器将全局地址映射到沿着数据路径的某个内部模块目标端口朝向第二个外围模块。

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