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    UNIVERSAL MEMORY SOCKET AND CARD AND SYSTEM FOR USING THE SAME
    4.
    发明申请
    UNIVERSAL MEMORY SOCKET AND CARD AND SYSTEM FOR USING THE SAME 审中-公开
    通用存储器插件和使用它的卡和系统

    公开(公告)号：US20090020608A1

    公开(公告)日：2009-01-22

    申请号：US12062287

    申请日：2008-04-03

    申请人： Jon C. R. Bennett ,  Kevin D. Drucker ,  Stephen Fischer ,  William Githens ,  Michael Kolodchak

    发明人： Jon C. R. Bennett ,  Kevin D. Drucker ,  Stephen Fischer ,  William Githens ,  Michael Kolodchak

    IPC分类号： G06K7/06

    CPC分类号： G06F13/387 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/10159

    摘要： A memory circuit card is described, where the electrical and physical interface between the circuit card and a motherboard bus is independent of the memory type installed on the circuit card. The power supply voltage provided by the mother board is independent of the memory type, and persistent and non-persistent memory types may be used on a plurality of circuit cards installed on the motherboard. The power status of at least portions of the interfaces of the circuit card may be controlled at a future time based on signals received at an input of circuit card.

    摘要翻译： 描述了存储器电路卡，其中电路卡和母板总线之间的电气和物理接口独立于安装在电路卡上的存储器类型。 由母板提供的电源电压独立于存储器类型，并且可以在安装在主板上的多个电路卡上使用持久和非持久存储器类型。 基于在电路卡的输入端接收到的信号，电路卡的接口的至少部分的电源状态可以在未来的时间被控制。

    Method and system for internal data loop back in a high data rate switch
    5.
    发明申请
    Method and system for internal data loop back in a high data rate switch 审中-公开
    内部数据的方法和系统循环回到高数据速率开关

    公开(公告)号：US20070183415A1

    公开(公告)日：2007-08-09

    申请号：US11346671

    申请日：2006-02-03

    申请人： Stephen Fischer ,  Lampros Kalampoukas ,  Anand Kanagala

    发明人： Stephen Fischer ,  Lampros Kalampoukas ,  Anand Kanagala

    IPC分类号： H04L12/56 ,  H04J3/16

    CPC分类号： H04L49/3009 ,  H04L49/602

    摘要： A method and system for internal data loop back in a packet switch is provided. In some instances, the switch may be required to process multiple layers of a header within the data packet, such as when data is transferred over the network encapsulated with a TCP header at the Transport Layer to form a TCP packet, then encapsulated with an IP header at the Network Layer to form an IP packet, then encapsulated with one or more MPLS headers to form a MPLS packet, and then encapsulated with an Ethernet header at the Link Layer to form an Ethernet packet. In such an instance, the data packet can be iteratively processed by the packet switch using an internal loop back technique. An internal loop back may be accomplished by using a header providing internal routing instructions resulting in the data packet being routed directly from an egress queue back to an ingress queue whereupon the lower levels of the header can be processed.

    摘要翻译： 提供了一种在数据包交换机中循环回内部数据的方法和系统。 在一些情况下，可能需要交换机来处理数据分组内的报头的多层，例如当数据通过传输层上用TCP报头封装的网络传输以形成TCP分组时，然后用IP封装 在网络层的头部形成一个IP包，然后用一个或多个MPLS头封装形成一个MPLS包，然后用链路层的以太网头封装形成一个以太网包。 在这种情况下，数据分组可以使用内部循环技术由分组交换机进行迭代处理。 可以通过使用提供内部路由指令的报头来实现内部循环，该报头导致数据分组从出口队列直接路由到入口队列，从而可以处理报头的较低级别。

    Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
    6.
    发明授权
    Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit 失效
    总线仲裁与主控单元控制总线和锁定从属单元，可以放弃其他主机的总线，同时保持从单元的锁定

    公开(公告)号：US5467295A

    公开(公告)日：1995-11-14

    申请号：US876577

    申请日：1992-04-30

    申请人： Bruce Young ,  Dave Carson ,  Norman Rasmussen ,  Stephen Fischer ,  Jeffrey Rabe

    发明人： Bruce Young ,  Dave Carson ,  Norman Rasmussen ,  Stephen Fischer ,  Jeffrey Rabe

    IPC分类号： G06F13/364 ,  G06F13/36

    CPC分类号： G06F13/364

    摘要： A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it. Signal line LOCK# is owned by only one master agent at a time. Although the LOCK# signal must be obtained by acquiring the bus while LOCK# is high, ownership of the line is maintained as long as LOCK# is held low. Therefore, a master agent can own the lock while another master uses the bus.

    摘要翻译： 一种计算机总线，其使得总线主控代理能够向/从从属代理发送/接收数据的突发，而不事先确定要传送的数据字的数量，或甚至可以传送的最大数量的数据字。 主机，从机或总线仲裁器可以随时以最小的开销终止突发。 此外，主机或从机可以通过添加等待状态来抑制数据传输的速度。 分布式地址解码由耦合到总线的每个代理执行。 每个代理人必须要求主人指示的交易。 如果没有代理人在预定数量的时钟周期内要求交易，减法解码设备可以默认地要求交易。 总线还包括总线锁，其中每个总线从属代理可能能够进入锁定状态，并且一旦处于锁定状态，则拒绝除了被锁定的主代理发起的所有访问之外的所有访问。 信号线LOCK＃一次只由一个主代理拥有。 虽然LOCK＃信号必须通过在LOCK＃为高电平时获取总线而获得，但只要LOCK＃保持低电平，就保持线路的所有权。 因此，主代理可以拥有锁，而另一个主机使用总线。

    System and method for limiting exposure of hardware failure information for a secured execution environment
    7.
    发明申请
    System and method for limiting exposure of hardware failure information for a secured execution environment 有权
    用于限制安全执行环境的硬件故障信息暴露的系统和方法

    公开(公告)号：US20060075312A1

    公开(公告)日：2006-04-06

    申请号：US10956322

    申请日：2004-09-30

    申请人： Stephen Fischer ,  Shamanna Datta

    发明人： Stephen Fischer ,  Shamanna Datta

    IPC分类号： G06F11/00

    CPC分类号： G06F21/74 ,  G06F2221/2101

    摘要： A method and apparatus for limiting the exposure of hardware failure information is described. In one embodiment, an error reporting system of a processor may log various status and error address data into registers that retain their contents through a warm reset event. But the error reporting system of the processor may then determine whether the processor is operating in a trusted or secure mode. If not, then the processor's architectural state variables may also be logged into registers. But if the processor is operating in a trusted or secure mode, then the logging of the architectural state variables may be inhibited, or flagged as invalid.

    摘要翻译： 描述了用于限制硬件故障信息的暴露的方法和装置。 在一个实施例中，处理器的错误报告系统可以将各种状态和错误地址数据记录到通过热复位事件保留其内容的寄存器中。 但是处理器的错误报告系统然后可以确定处理器是否以可信任或安全模式操作。 如果没有，则处理器的体系结构状态变量也可能被记录到寄存器中。 但是，如果处理器以可信任或安全模式运行，则可能会禁止对架构状态变量的日志记录或标记为无效。

    Bridge buffer management by bridge interception of synchronization events
    8.
    发明授权
    Bridge buffer management by bridge interception of synchronization events 失效
    桥接缓冲器管理通过桥接拦截同步事件

    公开(公告)号：US5941964A

    公开(公告)日：1999-08-24

    申请号：US480953

    申请日：1995-06-07

    申请人： Bruce Young ,  Jeff Rabe ,  Stephen Fischer

    发明人： Bruce Young ,  Jeff Rabe ,  Stephen Fischer

    IPC分类号： G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/405

    摘要： A bus bridge which intercepts synchronization events and selectively flushes data in buffers within the bridge is disclosed. The bridge insures data consistency by actively intercepting synchronization events, including, interrupts, processor accesses of a control status registers, and I/O master accesses of shared memory space. Interrupt signals may be routed through the bridge, which includes a bridge control unit comprised of state machine logic for managing data transfers through the bridge. In response to an interrupt signal from an agent on a bus, the bridge control unit flushes posted data before allowing a processor to process the interrupt signal. The bridge control unit further requires that the bridge complete all posted writes generated from a first bus before the bridge accepts a read generated from a second bus. The bridge control unit additionally insures strict ordering of accesses through the bridge. Data consistency is thereby realized without requiring the bridge to participate in the cache coherency protocol of the primary bus.

    摘要翻译： 公开了一种拦截同步事件并有选择地刷新桥内缓冲器中的数据的总线桥。 该桥通过主动拦截同步事件，包括中断，控制状态寄存器的处理器访问和共享存储空间的I / O主机访问来保证数据一致性。 中断信号可以通过桥接器路由，其包括由用于管理通过桥接器的数据传输的状态机逻辑组成的桥接控制单元。 响应于来自总线上的代理的中断信号，桥接控制单元在允许处理器处理中断信号之前刷新发布的数据。 桥接控制单元还要求桥接器在桥接受从第二总线产生的读取之前，完成从第一总线产生的所有发布的写入。 桥梁控制单元另外确保通过桥梁的严格顺序访问。 从而实现数据一致性，而不需要桥接器来参与主总线的高速缓存一致性协议。

    Locking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains locked
    9.
    发明授权
    Locking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains locked 失效
    使用主设备的外围组件互连的锁定协议，在放弃总线控制之后保持锁定信号的断言，使得从设备保持锁定

    公开(公告)号：US5887194A

    公开(公告)日：1999-03-23

    申请号：US472069

    申请日：1995-06-05

    申请人： Dave Carson ,  Bruce Young ,  Norman Rasmussen ,  Stephen Fischer ,  Jeffrey Rabe

    发明人： Dave Carson ,  Bruce Young ,  Norman Rasmussen ,  Stephen Fischer ,  Jeffrey Rabe

    IPC分类号： G06F13/364 ,  G06F13/14 ,  G06F13/20

    CPC分类号： G06F13/364

    摘要： A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it. Signal line LOCK# is owned by only one master agent at a time. Although the LOCK# signal must be obtained by acquiring the bus while LOCK# is high, ownership of the line is maintained as long as LOCK# is held low. Therefore, a master agent can own the lock while another master uses the bus.

    摘要翻译： 一种计算机总线，其使得总线主控代理能够向/从从属代理发送/接收数据的突发，而不事先确定要传送的数据字的数量，或甚至可以传送的最大数量的数据字。 主机，从机或总线仲裁器可以随时以最小的开销终止突发。 此外，主机或从机可以通过添加等待状态来抑制数据传输的速度。 分布式地址解码由耦合到总线的每个代理执行。 每个代理人必须要求主人指示的交易。 如果没有代理人在预定数量的时钟周期内要求交易，减法解码设备可以默认地要求交易。 总线还包括总线锁，其中每个总线从属代理可能能够进入锁定状态，并且一旦处于锁定状态，则拒绝除了被锁定的主代理发起的所有访问之外的所有访问。 信号线LOCK＃一次只由一个主代理拥有。 虽然LOCK＃信号必须通过在LOCK＃为高电平时获取总线而获得，但只要LOCK＃保持低电平，就保持线路的所有权。 因此，主代理可以拥有锁，而另一个主机使用总线。

    Substituted amino heterocycles as vr-1 antagonists for treating pain
    10.
    发明申请
    Substituted amino heterocycles as vr-1 antagonists for treating pain 审中-公开

    公开(公告)号：US20060154930A1

    公开(公告)日：2006-07-13

    申请号：US10545877

    申请日：2004-02-20

    申请人： Rebecca Brown ,  Frank Burkamp ,  Victoria Doughty ,  Stephen Fischer ,  Gregory Hollingworth ,  A. Jones ,  Timothy Sparey

    发明人： Rebecca Brown ,  Frank Burkamp ,  Victoria Doughty ,  Stephen Fischer ,  Gregory Hollingworth ,  A. Jones ,  Timothy Sparey

    IPC分类号： C07D487/04 ,  A61K31/503

    CPC分类号： C07D471/04 ,  C07D487/04

    摘要： The present invention provides compounds of formula I: in which: one of T1 and T4 is N and the other is C; T2 and T3 are independently N or C(CH2)nR2; X, Y and Z are independently N or C(CH2)nR3; R1 is Ar1 or R1 is C1-6alkyl optionally substituted with one or two groups Ar1; Ar1 is an optionally substituted cyclohexyl, piperidinyl, piperazinyl, morpholinyl, adamantyl, phenyl, naphthyl, a six membered heteroaromatic ring containing one, two or three nitrogen atoms, a five-membered heteroaromatic ring containing one, two, three or four heteroatoms chosen from O, N and S, at most one O or S atom being present, or a nine- or ten-membered bicyclic heteroaromatic ring in which phenyl or a six-membered heteroaromatic ring as defined above is fused to a six- or five-membered heteroaromatic ring as defined above; Ar is an optionally substituted phenyl, a six-membered heteroaromatic ring containing one, two or three nitrogen atoms or a five-membered heteroaromatic ring containing one, two, three or four heteroatoms chosen from O, N and S, at most one heteroatom being O or S, Ar being optionally substituted by one, two or three groups chosen from halogen, CF3, OCF3, C1-6-alkyl, C2-6alkenyl, C2-6alkynyl, nitro, cyano, isonitrile, hydroxy, C1-6alkoxy, C1-6alkylthio, —NR6R7, —CONR6R7, —COH, CO2H, C1-6alkoxycarbonyl, haloC1-4alkyl, hydroxyC1-6alkyl, aminoC1-6alkyl, C1-4alkylcarbonyl and a five-membered heteroaromatic ring containing one, two, three or four heteroatoms chosen from O, N and S, at most one heteroatom being O or S, optionally substituted by C1-6alkyl, halogen, amino, hydroxy or cyano; or a pharmaceutically acceptable salt thereof as a VR-1 ligand; pharmaceutical compositions comprising it; its use in therapy; use of it in the manufacture of a medicament to treat pain; and methods of treating subjects suffering from pain.