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126 条记录 (耗时 0.023 秒)

    BPSG, SA-CVD liner/P-HDP gap fill
    41.
    发明授权
    BPSG, SA-CVD liner/P-HDP gap fill 有权
    BPSG，SA-CVD衬垫/ P-HDP间隙填充

    公开(公告)号：US06613657B1

    公开(公告)日：2003-09-02

    申请号：US10231133

    申请日：2002-08-30

    申请人： Minh Van Ngo ,  Dawn Hopper ,  Wenmei Li ,  Kelwin King Wai Ko ,  Kuo-Tung Chang ,  Tyagamohan Gottipati

    发明人： Minh Van Ngo ,  Dawn Hopper ,  Wenmei Li ,  Kelwin King Wai Ko ,  Kuo-Tung Chang ,  Tyagamohan Gottipati

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： Device leakage due to spacer undercutting is remedied by depositing a BPSG, SA-CVD oxide liner and flowing it into the undercut regions, followed by gap filling with a P-doped HDP oxide layer. Embodiments include depositing a BPSG, SA-CVD oxide liner containing 4 to 6 wt.% boron, at a thickness of 1,000 Å to 1,800 Å, over closely spaced apart non-volatile transistors and heating during or subsequent to deposition to flow the BPSG, SA-CVD oxide liner into the undercut regions of the sidewall spacers of the gate stacks. Gap filling is then completed by depositing the layer of P-doped HDP at a thickness of 6,000 Å to 10,000 Å.

    摘要翻译： 通过沉积BPSG，SA-CVD氧化物衬垫并将其流入底切区域，随后用P掺杂的HDP氧化物层填充间隙来补救由间隔物底切造成的器件泄漏。 实施方案包括在紧密间隔开的非易失性晶体管上沉积厚度为1,000至1,800的含有4至6重量％硼的BPSG，SA-CVD氧化物衬垫，并在沉积期间或之后加热以使BPSG流动， SA-CVD氧化物衬垫进入栅堆叠的侧壁间隔物的底切区域。 然后通过沉积厚度为6,000至10,000的P掺杂HDP层完成间隙填充。

    Method of making and accessing split gate memory device
    42.
    发明授权
    Method of making and accessing split gate memory device 失效
    制造和访问分闸门存储器件的方法

    公开(公告)号：US5824584A

    公开(公告)日：1998-10-20

    申请号：US876326

    申请日：1997-06-16

    申请人： Wei-Ming Chen ,  Lee Z. Wang ,  Kuo-Tung Chang ,  Craig Swift

    发明人： Wei-Ming Chen ,  Lee Z. Wang ,  Kuo-Tung Chang ,  Craig Swift

    IPC分类号： H01L21/8239 ,  H01L27/105 ,  H01L21/336

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  Y10S438/933

    摘要： A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.

    摘要翻译： 示出了具有控制栅极（14）和侧壁选择栅极（28）的非易失性存储器。 侧壁选择栅极（28）与半导体掺杂氧化物（20）结合形成以形成非易失性存储单元（7）。 用于掺杂氧化物层（20）的半导体元件通常将包括硅或锗。 通过在掺杂氧化物（20）中存储电子来对非易失性存储单元（7）进行编程，并且使用带 - 带隧道进行擦除。

    Method for operating a memory array
    43.
    发明授权
    Method for operating a memory array 失效
    操作存储器阵列的方法

    公开(公告)号：US5706228A

    公开(公告)日：1998-01-06

    申请号：US603939

    申请日：1996-02-20

    申请人： Kuo-Tung Chang ,  Craig A. Cavins ,  Ko-Min Chang ,  Bruce L. Morton ,  George L. Espinor

    发明人： Kuo-Tung Chang ,  Craig A. Cavins ,  Ko-Min Chang ,  Bruce L. Morton ,  George L. Espinor

    IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C11/40

    CPC分类号： G11C16/3427 ,  G11C16/0433 ,  G11C16/10

    摘要： A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.

    摘要翻译： 具有选定的存储单元（10）和未选择的存储单元（30）的存储器阵列（25）被编程和读取。 存储器阵列（25）中的每个存储单元包含隔离晶体管（22）和浮动栅极晶体管（23）。 为了对所选择的存储单元（10）进行编程，将编程电压施加到控制栅极线（21），漏极线（14），隔离线（19）和源极线（12）。 为了减小漏极干扰问题的影响，未选择的存储单元（30）的栅极端子（32）被保持在正电压。 为了读取所选择的存储单元（10），读取电压被施加到未选择存储单元（30）的隔离栅极线（31），其确保未选择的存储单元（30）不导通或有助于漏电流和功耗 在读操作期间。

    Dual charge storage node memory device and methods for fabricating such device
    44.
    发明授权
    Dual charge storage node memory device and methods for fabricating such device 有权
    双电荷存储节点存储器件及其制造方法

    公开(公告)号：US08183623B2

    公开(公告)日：2012-05-22

    申请号：US13075047

    申请日：2011-03-29

    申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    IPC分类号： H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  Y10S438/954

    摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

    摘要翻译： 提供了一种双节点存储器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。 这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。 在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。 沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。 侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。 在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

    Memory device and methods for its fabrication
    47.
    发明授权
    Memory device and methods for its fabrication 有权
    存储器件及其制造方法

    公开(公告)号：US07564091B2

    公开(公告)日：2009-07-21

    申请号：US12199692

    申请日：2008-08-27

    申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

    发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

    摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

    摘要翻译： 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

    Shallow trench isolation approach for improved STI corner rounding
    48.
    发明授权
    Shallow trench isolation approach for improved STI corner rounding 有权
    浅沟隔离方法可改善STI拐角四舍五入

    公开(公告)号：US07439141B2

    公开(公告)日：2008-10-21

    申请号：US10277395

    申请日：2002-10-22

    申请人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

    发明人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76235

    摘要： A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

    摘要翻译： 公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。 该方法包括将沟槽蚀刻到有源区域之间的硅衬底中，并在沟槽上执行双衬层氧化工艺。 该方法还包括对活性区域进行双重牺牲氧化处理，其中沟槽的角通过四个氧化过程基本上被圆化。

    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
    49.
    发明申请
    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
    通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀

    公开(公告)号：US20080171416A1

    公开(公告)日：2008-07-17

    申请号：US11653649

    申请日：2007-01-12

    申请人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

    发明人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

    摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。 在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。 对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。 然后在核心单元之间部分蚀刻捕获层。 进行捕获层上的氧化物的偏移。 并形成顶部氧化物。 顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。