公开(公告)号：US20080290421A1

公开(公告)日：2008-11-27

申请号：US11807127

申请日：2007-05-25

Applicant: Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/76844 ,  H01L21/7685 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅极电介质相邻的源极/漏极区域; 源/漏区上的硅化物区; 硅化物区域的顶部和物理接触处的金属层; 金属层上的层间电介质（ILD）; 和ILD的接触开口。 金属层通过接触开口露出。 金属层进一步在ILD下延伸。 半导体结构还包括接触开口中的接触。

公开(公告)号：US07429975B2

公开(公告)日：2008-09-30

申请号：US10996419

申请日：2004-11-26

Applicant: Wen-Chin Lee ,  Shang-Hao Chen

Inventor： Wen-Chin Lee ,  Shang-Hao Chen

IPC: G09G5/00

CPC classification number: G06F3/0346 ,  G05G9/047 ,  G06F3/0362

Abstract: A magnetic oscillation metric controller with return design comprised of a scrolling wheel mechanism, a dancer, a permanent magnet, a Hall sensor and a return structure to drive the permanent magnet by oscillation of the scrolling wheel mechanism to generate signals of changed magnetic fields resulted from displacement for achieving metric control purpose; and the return structure including an elastic stick to facilitate return after lateral or longitudinal displacement.

Abstract translation: 具有返回设计的磁振荡度量控制器包括滚动轮机构，浮动机构，永磁体，霍尔传感器和返回结构，以通过滚动轮机构的振荡来驱动永磁体，以产生由 实现度量控制目的的排量 并且返回结构包括弹性棒，以便于在横向或纵向位移之后返回。

公开(公告)号：US20080185659A1

公开(公告)日：2008-08-07

申请号：US11703365

申请日：2007-02-07

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L29/94 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.

Abstract translation: 具有被超应力层覆盖的至少一个晶体管的半导体器件及其制造方法。 在NMOS器件中，超应力层包括源极和漏极区域上的拉伸应力膜，以及多个区域上的压应力膜。 在PMOS器件中，超应力层包括源极和漏极区域上的压缩应力膜和在多个区域上的拉伸应力膜。 在优选实施例中，半导体器件包括PMOS晶体管和形成CMOS器件并被超压应力层覆盖的NMOS晶体管。

公开(公告)号：US07394136B2

公开(公告)日：2008-07-01

申请号：US11194084

申请日：2005-07-29

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

IPC: H01L21/00

CPC classification number: H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7842

Abstract: A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

Abstract translation: 公开了一种改进的驱动电流的高性能半导体器件及其制造方法。 半导体器件具有构建在有源区上的源极和漏极区域，器件的长度与其宽度不同。 在有源区周围制造一个或多个隔离区域，然后用退火处理后其体积收缩率超过0.5％的预定隔离材料填充隔离区域。 在有源区上形成栅电极，并且在栅电极旁边形成一个或多个电介质间隔物。 然后，接触蚀刻停止层放置在器件上，其中隔离区，间隔物和接触蚀刻层有助于调制施加在有源区上的净应变，以便改善驱动电流。

公开(公告)号：US07354830B2

公开(公告)日：2008-04-08

申请号：US11377105

申请日：2006-03-16

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Yee-Chia Yeo

IPC: H01L21/8234

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

Abstract translation: 提供一种制造集成电路的方法。 第一栅介质部分形成在第一晶体管区域中的衬底上。 第一栅介质部分包括第一高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 在第二晶体管区域中的衬底上形成第二栅介质部分。 第二栅介质部分包括第一高电容率介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度不同于第一等效氧化硅厚度。

公开(公告)号：US07338299B1

公开(公告)日：2008-03-04

申请号：US11567593

申请日：2006-12-06

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: H01R12/00

CPC classification number: H05K3/3442 ,  H05K2201/09181 ,  H05K2201/10636 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613

Abstract: An exemplary surface mounted electronic component has block body including a bottom soldering surface, a top surface and a peripheral wall having a first peripheral wall portion and a second peripheral wall portion. The bottom soldering surface defines a first soldering area and a second soldering area. The first peripheral wall portion adjoins the first soldering area and has at least a first cutout defined between the first peripheral wall portion and the first soldering area. The second peripheral wall portion adjoins the second soldering area and has at least a second cutout defined between the second peripheral wall portion and the second soldering area. When the surface mounted electronic component is soldered, the melting solder can climb up the cutouts of the sidewall due to capillary effect and ‘chimney effect’, thereby avoiding ‘tombstoning’.

Abstract translation: 示例性的表面安装电子部件具有块体，其包括底部焊接表面，顶表面和具有第一周壁部分和第二周壁部分的周壁。 底部焊接表面限定第一焊接区域和第二焊接区域。 所述第一周壁部分邻接所述第一焊接区域，并且至少具有限定在所述第一周壁部分和所述第一焊接区域之间的第一切口。 所述第二周壁部分邻接所述第二焊接区域，并且在所述第二周壁部分和所述第二焊接区域之间具有至少第二切口。 当表面安装的电子部件被焊接时，由于毛细管效应和“烟囱效应”，熔化焊料可以爬上侧壁的切口，从而避免“墓碑”。

公开(公告)号：US07268024B2

公开(公告)日：2007-09-11

申请号：US10999564

申请日：2004-11-29

Applicant: Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L21/84

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7854

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Abstract translation: 根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。 在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。 包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。 例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

公开(公告)号：US20070161206A1

公开(公告)日：2007-07-12

申请号：US11586936

申请日：2006-10-26

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

Abstract translation: 公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

公开(公告)号：US07208754B2

公开(公告)日：2007-04-24

申请号：US11114981

申请日：2005-04-26

Applicant: Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.

Abstract translation: 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于衬底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。

公开(公告)号：US20070052027A1

公开(公告)日：2007-03-08

申请号：US11220176

申请日：2005-09-06

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC: H01L27/01

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

Abstract: A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

Abstract translation: 提供CMOS器件。 半导体器件包括衬底，衬底具有第一区域和第二区域，第一区域具有由包括{i，j，k}的米勒指数族代表的第一晶体取向，第二区域具有第二晶体取向 代表了包含{l，m，n}的米勒指数族，其中l 2+ + m 2 + 2 + 2 2 / 2 + 2＆lt; 2＆gt; 2＆gt; 2＆lt; 2＆gt; 替代实施例还包括形成在第一区域上的NMOSFET和形成在第二区域上的PMOSFET。 实施例还包括由NMOSFET或PMOSFET中的至少一个形成的肖特基接触。