公开(公告)号：US6018490A

公开(公告)日：2000-01-25

申请号：US169332

申请日：1998-10-09

申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

IPC分类号： G01R31/3185 ,  G11C8/12 ,  H03K19/094 ,  H03K19/173 ,  H03K19/177 ,  G11C13/00

CPC分类号： H03K19/09429 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17792 ,  G01R31/318516

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

公开(公告)号：US5883850A

公开(公告)日：1999-03-16

申请号：US664919

申请日：1996-06-18

申请人： Fung Fung Lee ,  Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

发明人： Fung Fung Lee ,  Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

IPC分类号： G11C8/12 ,  H03K19/173 ,  H03K19/177 ,  G11C13/00

CPC分类号： H03K19/17736 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

公开(公告)号：US5828229A

公开(公告)日：1998-10-27

申请号：US847004

申请日：1997-05-01

申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

IPC分类号： G01R31/3185 ,  G11C8/12 ,  G11C8/16 ,  G11C29/32 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737 ,  G11C29/32 ,  G11C8/12 ,  G11C8/16 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17764 ,  G01R31/318516

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.

摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。 随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。 此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

公开(公告)号：US5764583A

公开(公告)日：1998-06-09

申请号：US852015

申请日：1997-05-06

申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

IPC分类号： G01R31/3185 ,  G11C8/12 ,  H03K19/094 ,  H03K19/173 ,  H03K19/177 ,  G11C13/00

CPC分类号： H03K19/09429 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17792 ,  G01R31/318516

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

公开(公告)号：US5633830A

公开(公告)日：1997-05-27

申请号：US555106

申请日：1995-11-08

申请人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff

发明人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff

IPC分类号： G01R31/3185 ,  G11C8/12 ,  G11C8/16 ,  G11C29/32 ,  H03K19/173 ,  H03K19/177 ,  G11C7/00

CPC分类号： H03K19/1737 ,  G11C29/32 ,  G11C8/12 ,  G11C8/16 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17764 ,  G01R31/318516

摘要： A relatively large block of random access memory ("RAM") may be provided on a programmable logic array integrated circuit device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.

摘要翻译： 可以在可编程逻辑阵列集成电路装置上提供相对较大的随机存取存储器块（“RAM”），用于在设备操作期间用作只读存储器（“ROM”）或RAM以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。 此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

公开(公告)号：US5555214A

公开(公告)日：1996-09-10

申请号：US555110

申请日：1995-11-08

申请人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang

发明人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/103 ,  G11C7/22

摘要： A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesired reading and writing.

摘要翻译： 提供了串行读取和写入随机存取存储器阵列的方法。 尽管读/写输入随着编程数据被输入到输入缓冲器而不断变化，但读/写控制电路可以防止不断变化的读/写输入引起不期望的读和写。

公开(公告)号：US08982160B2

公开(公告)日：2015-03-17

申请号：US12761479

申请日：2010-04-16

申请人： Jadine N. Yee ,  Joel Bernarte ,  Janet L. Dobson ,  Giridhar D. Mandyam ,  Joseph Huang

发明人： Jadine N. Yee ,  Joel Bernarte ,  Janet L. Dobson ,  Giridhar D. Mandyam ,  Joseph Huang

IPC分类号： G09G5/00 ,  G06F3/01 ,  G06F3/0488

CPC分类号： G06F3/013 ,  G06F3/04886 ,  G06F2203/04805

摘要： Embodiments provide a user interface for computing devices equipped with a touchscreen user interface/display and a digital camera that enhances a portion of a displayed image within a user's gaze. A user may calibrate their mobile device by touching a portion of the touchscreen with one or more fingers and following a moving image on the display with their eyes. The mobile device may track where a user is looking, and if the user is looking at the mobile device display, a portion of the display in the vicinity of the user's gaze may be enhanced in size. In an embodiment, if the user is looking at a virtual keyboard, key icons near the user's gaze may be increased in size commensurate with the user's finger tip size. In this manner, a user can accurately select individual keys in a virtual keyboard that fits within a mobile device display.

摘要翻译： 实施例提供了一种用于装备有触摸屏用户界面/显示器和数字照相机的计算设备的用户界面，该数字照相机增强了用户目光中的显示图像的一部分。 用户可以通过用一个或多个手指触摸触摸屏的一部分并且用他们的眼睛在显示器上跟随运动图像来校准他们的移动设备。 移动设备可以跟踪用户正在寻找的位置，并且如果用户正在查看移动设备显示，则在用户的注视附近的显示器的一部分的大小可以被增强。 在一个实施例中，如果用户正在查看虚拟键盘，则用户的注视附近的键图标的大小可以与用户的指尖尺寸相对应地增大。 以这种方式，用户可以准确地选择适合于移动设备显示内的虚拟键盘中的各个键。

公开(公告)号：US08760876B2

公开(公告)日：2014-06-24

申请号：US13405268

申请日：2012-02-25

申请人： Joseph Huang

发明人： Joseph Huang

IPC分类号： H05K1/14

CPC分类号： H05K5/0278

摘要： A USB memory stick includes a metal shell structure defining opposing top opening and bottom opening and a locating hole, a PC board formed of a USB interface circuit and a memory chip package, and a tray, which includes a support panel supporting the PC board, a clip extended from one side of the support panel and clamped on the memory chip package of the PC board, a spring plate extended from the clip and pressed on the PC board against the support panel, and an oblique retaining leaf obliquely extended from the spring plate and engaged into the locating hole of the metal shell structure.

摘要翻译： USB记忆棒包括限定相对的顶部开口和底部开口的金属壳结构和定位孔，由USB接口电路和存储芯片封装形成的PC板，以及包括支撑PC板的支撑板的托盘， 从支撑板的一侧延伸并夹在PC板的存储芯片封装上的夹子，从夹子延伸并弹压在PC板上抵靠支撑板的弹簧板，以及从弹簧倾斜延伸的倾斜保持叶片 并接合到金属外壳结构的定位孔中。

公开(公告)号：US08689598B2

公开(公告)日：2014-04-08

申请号：US12646956

申请日：2009-12-23

申请人： Joseph Huang

发明人： Joseph Huang

IPC分类号： B21D31/02

CPC分类号： B21K23/00 ,  B21D31/02 ,  B21K25/00 ,  H05K5/0278

摘要： A method of forming a tenon on one side of a metal plate member by means of punching the wall of one side of the metal plate member with a punch or punches to form a protrusion and then punching the protrusion with a punch rod to extend the height of the protrusion and to deform the protrusion into a tubular configuration.

摘要翻译： 通过用冲头或冲头冲压金属板构件的一侧的壁来形成榫头在金属板构件的一侧上的方法，以形成突起，然后用冲杆冲压突起以将高度 并使突起变形成管状构造。

公开(公告)号：US08593195B1

公开(公告)日：2013-11-26

申请号：US13614526

申请日：2012-09-13

申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

IPC分类号： H03H11/16

CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。