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241 条记录 (耗时 0.03 秒)

    Magneto-resistive memory cell structures with improved selectivity
    41.
    发明授权
    Magneto-resistive memory cell structures with improved selectivity 有权
    具有改善选择性的磁阻存储单元结构

    公开(公告)号：US06920064B2

    公开(公告)日：2005-07-19

    申请号：US10804584

    申请日：2004-03-16

    申请人： Theodore Zhu ,  Yong Lu ,  Anthony Arrott

    发明人： Theodore Zhu ,  Yong Lu ,  Anthony Arrott

    IPC分类号： G11C11/00 ,  G11C11/15 ,  G11C11/14

    CPC分类号： G11C11/16 ,  G11C11/15

    摘要： A magneto-resistive memory comprises magneto-resistive memory cells comprising two pinned magnetic layers on one side of a free magnetic layer. The pinned magnetic layers are formed with anti-parallel magnetization orientations such that a net magnetic moment of the two layers is substantially zero. The influence of pinned magnetic layers on free magnetic layer magnetization orientations is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.

    摘要翻译： 磁阻存储器包括在自由磁性层的一侧上包括两个固定磁性层的磁阻存储器单元。 被钉扎的磁性层形成为具有反平行磁化取向，使得两层的净磁矩基本为零。 固有磁性层对自由磁性层磁化取向的影响基本上消除了，从而增加了开关行为的可预测性和增加了存储单元的写入选择性。

    Magnetoresistive random access memory (MRAM) cell patterning
    42.
    发明授权
    Magnetoresistive random access memory (MRAM) cell patterning 有权
    磁阻随机存取存储器（MRAM）细胞图案化

    公开(公告)号：US06677165B1

    公开(公告)日：2004-01-13

    申请号：US10393713

    申请日：2003-03-20

    申请人： Yong Lu ,  Theodore Zhu

    发明人： Yong Lu ,  Theodore Zhu

    IPC分类号： H01L218242

    CPC分类号： H01L27/222 ,  H01L43/12 ,  Y10S438/951

    摘要： A process that advantageously forms MRAM cells without the application of ion beam milling processes. Unlike conventional processes that rely on ion beam milling processes to remove materials from a magnetoresistive sandwich from areas other than areas that will later form MRAM cell bodies, this process forms a layer of photoresist over areas other than those areas that correspond to MRAM cell bodies. The photoresist is lifted off after the deposition of a magnetoresistive sandwich that forms the MRAM cell bodies, thereby safely removing the magnetoresistive sandwich from undesired areas while maintaining the magnetoresistive sandwich in the areas corresponding to MRAM cell bodies.

    摘要翻译： 有利地形成MRAM电池而不施加离子束研磨工艺的方法。 不同于依靠离子束研磨工艺从除了稍后形成MRAM单元体的区域之外的区域从磁阻三明治去除材料的常规工艺，该工艺在除了对应于MRAM单元体的那些区域之外的区域上形成光致抗蚀剂层。 在形成MRAM单元体的磁阻三明治的沉积之后，光致抗蚀剂被剥离，从而从不期望的区域安全地去除磁阻三明治，同时在对应于MRAM单元体的区域中保持磁阻三明治。

    DC/low frequency sub-atto signal level measurement circuit
    43.
    发明授权
    DC/low frequency sub-atto signal level measurement circuit 有权
    直流/低频子信号电平测量电路

    公开(公告)号：US06556025B1

    公开(公告)日：2003-04-29

    申请号：US09595367

    申请日：2000-06-16

    申请人： Arokia Nathan ,  Yong Lu ,  Tajinder Manku

    发明人： Arokia Nathan ,  Yong Lu ,  Tajinder Manku

    IPC分类号： G01R2726

    CPC分类号： G01R19/2509 ,  G01R27/2605 ,  G01R29/24

    摘要： A method of measuring changes in signal level output of an integrated circuit sensor by providing a direct current (DC) or low frequency (AC) bias to the sensor and placing a floating gate semiconductor device on-chip and coupling the floating gate of the semiconductor device with the sensor. As a result, changes in signal level output of the sensor modulate charge at the gate. The semiconductor device in turn converts the modulated charge at the gate into output signals proportional to the changes in the signal level output. The measurement method provides a resolution in the sub-atto range.

    摘要翻译： 一种通过向传感器提供直流（DC）或低频（AC）偏压并且将浮置栅极半导体器件放置在芯片上并耦合半导体的浮置栅极来测量集成电路传感器的信号电平输出的变化的方法 设备与传感器。 结果，传感器的信号电平输出的变化调制门的电荷。 半导体器件又将栅极处的调制电荷转换为与信号电平输出的变化成比例的输出信号。 测量方法提供了分数范围内的分辨率。

    Method and apparatus for writing data states to non-volatile storage devices
    44.
    发明授权
    Method and apparatus for writing data states to non-volatile storage devices 有权
    将数据状态写入非易失性存储设备的方法和装置

    公开(公告)号：US06178111B1

    公开(公告)日：2001-01-23

    申请号：US09455850

    申请日：1999-12-07

    申请人： Jeffrey Scott Sather ,  Theodore Zhu ,  Yong Lu

    发明人： Jeffrey Scott Sather ,  Theodore Zhu ,  Yong Lu

    IPC分类号： G11C1100

    CPC分类号： G11C11/15

    摘要： Disclosed are apparatus and methods for efficiently writing states to one or more magneto-resistive elements. In one embodiment, current switches are provided for directing a write current through a number of write lines to control the write state of the magneto-resistive elements. In another embodiment, a sense current is selectively controlled to control which magneto-resistive elements are written to a particular state. In both embodiments, a latching element may be used to sense the state of the magneto-resistive elements, and may assume a corresponding logic state.

    摘要翻译： 公开了用于有效地将状态写入一个或多个磁阻元件的装置和方法。 在一个实施例中，提供电流开关用于引导写入电流通过多个写入线以控制磁阻元件的写入状态。 在另一个实施例中，选择性地控制感测电流以控制将哪个磁阻元件写入特定状态。 在两个实施例中，锁存元件可用于感测磁阻元件的状态，并且可以采取相应的逻辑状态。

    Bipolar CMOS select device for resistive sense memory
    46.
    发明授权
    Bipolar CMOS select device for resistive sense memory 有权
    用于电阻读出存储器的双极CMOS选择器件

    公开(公告)号：US09030867B2

    公开(公告)日：2015-05-12

    申请号：US12502211

    申请日：2009-07-13

    申请人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    发明人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    IPC分类号： G11C11/00 ,  G11C11/34 ,  G11C13/00 ,  G11C11/16

    CPC分类号： G11C13/0004 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/76

    摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

    摘要翻译： 电阻式感测存储装置包括具有半导体衬底和设置在半导体衬底中并形成行或晶体管的多个晶体管的双极选择器件。 每个晶体管包括发射极触点和集电极触点。 每个集电极触点彼此电隔离，并且每个发射极触点彼此电隔离。 栅极触点沿发射极触点和集电极触点之间的沟道区域延伸。 基极触点设置在半导体衬底内，使得发射极触点和集电极触点位于栅极触点和基极触点之间。 电阻读出存储单元电耦合到每个集电极触点或发射极触点和位线。

    Bit line charge accumulation sensing for resistive changing memory
    49.
    发明授权
    Bit line charge accumulation sensing for resistive changing memory 有权
    电阻变化存储器的位线电荷累积检测

    公开(公告)号：US08638597B2

    公开(公告)日：2014-01-28

    申请号：US13476368

    申请日：2012-05-21

    申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

    摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

    摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

    Magnetic memory with separate read and write paths
    50.
    发明授权
    Magnetic memory with separate read and write paths 失效
    具有独立读写路径的磁记忆体

    公开(公告)号：US08520432B2

    公开(公告)日：2013-08-27

    申请号：US12974699

    申请日：2010-12-21

    申请人： Yong Lu ,  Hongyue Liu ,  Zheng Gao ,  Insik Jin ,  Dimitar V. Dimitrov

    发明人： Yong Lu ,  Hongyue Liu ,  Zheng Gao ,  Insik Jin ,  Dimitar V. Dimitrov

    IPC分类号： G11C11/14

    CPC分类号： H01L43/02 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

    摘要： Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.

    摘要翻译： 公开了具有分离的读和写路径的磁存储器。 磁存储器单元包括具有第一磁化取向的第一端部，具有第二磁化取向的相对的第二端部和第一端部与第二端部之间的中间部分的铁磁条，所述中间部分具有 自由磁化方向。 第一磁化取向与第二磁化取向相反。 隧道势垒将磁性参考层与形成磁性隧道结的中间部分分开。 位线电耦合到第二端部。 源极线电耦合到第一端部，并且读取线电耦合到磁性隧道结。