公开(公告)号：US5736438A

公开(公告)日：1998-04-07

申请号：US483411

申请日：1995-06-07

申请人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

发明人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L29/78654 ,  H01L27/1281 ,  Y10S257/903

摘要： In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

摘要翻译： 在TFT负载型的小型化的完全CMOS SRAM中，场效应薄膜晶体管（TFT）能够实现对存储单元的稳定的读/写操作并且可以降低其功耗。 形成在绝缘体上的场效应薄膜晶体管包括有源层和栅电极。 栅电极形成在有源层的沟道区上，其间具有栅极绝缘膜。 有源层由沟道区和源极/漏极区形成。 沟道区由单晶硅层形成，不包含晶界。 源/漏区由多晶硅层形成。 沟道区域的晶体缺陷密度小于109个/ cm 2。 薄膜晶体管的通道宽度为1μm，导通电流为0.25μA/μm，OFF电流为15fA /μm。 薄膜晶体管可以被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。

公开(公告)号：US09590099B2

公开(公告)日：2017-03-07

申请号：US14859447

申请日：2015-09-21

申请人： Bin Liu ,  Sun-Min Kim ,  Shigenobu Maeda

发明人： Bin Liu ,  Sun-Min Kim ,  Shigenobu Maeda

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  H01L29/10 ,  H01L29/06 ,  H01L21/324

CPC分类号： H01L29/7833 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

摘要： Semiconductor devices are provided including an active layer, a gate structure, a spacer, and a source/drain layer. The active layer is on the substrate and includes germanium. The active layer includes a first region having a first germanium concentration, and a second region on both sides of the first region. The second region has a top surface getting higher from a first portion of the second region adjacent to the first region toward a second portion of the second region far from the first region, and has a second germanium concentration less than the first germanium concentration. The gate structure is formed on the first region of the active layer. The spacer is formed on the second region of the active layer, and contacts a sidewall of the gate structure. The source/drain layer is adjacent to the second region of the active layer.

摘要翻译： 提供了包括有源层，栅极结构，间隔物和源极/漏极层的半导体器件。 有源层在基底上，包括锗。 有源层包括具有第一锗浓度的第一区域和位于第一区域两侧的第二区域。 第二区域具有从与第一区域相邻的第二区域的第一部分朝向远离第一区域的第二区域的第二部分更高的顶表面，并且具有小于第一锗浓度的第二锗浓度。 栅极结构形成在有源层的第一区域上。 间隔物形成在有源层的第二区域上，并与门结构的侧壁接触。 源极/漏极层与有源层的第二区域相邻。

公开(公告)号：US08962435B2

公开(公告)日：2015-02-24

申请号：US14508250

申请日：2014-10-07

申请人： Shigenobu Maeda ,  Hidenobu Fukutome ,  Young-Gun Ko ,  Joo-Hyun Jeong

发明人： Shigenobu Maeda ,  Hidenobu Fukutome ,  Young-Gun Ko ,  Joo-Hyun Jeong

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/7842 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02636 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

摘要翻译： 半导体器件可以包括有源区，其具有提供相对的源极和漏极区之间的沟道区的鳍部。 栅电极可以跨越在相对的源极和漏极区域之间的沟道区域上，并且第一和第二应变诱导结构可以在栅电极的相对侧上，并且可以被配置为在沟道区域上引起应变，其中第一和 第二应变诱导结构，其包括具有一对{111}晶体取向小面的相应的相对侧。

公开(公告)号：US20140203370A1

公开(公告)日：2014-07-24

申请号：US14161744

申请日：2014-01-23

申请人： Shigenobu Maeda ,  Tsukasa Matsuda ,  Hidenobu Fukutome

发明人： Shigenobu Maeda ,  Tsukasa Matsuda ,  Hidenobu Fukutome

IPC分类号： H01L29/78

CPC分类号： H01L29/665 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.

摘要翻译： 提供半导体器件。 所述半导体器件包括：衬底上的第一鳍片;与所述第一鳍片相交的所述衬底上形成的第一栅电极，所述第一栅电极两侧的所述第一鳍片上的第一升高源极/漏极;以及第一金属合金层 在第一升高的源极/漏极的上表面和侧壁上。

公开(公告)号：US08735238B2

公开(公告)日：2014-05-27

申请号：US13039525

申请日：2011-03-03

申请人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

发明人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

IPC分类号： H01L21/8238

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

摘要翻译： 公开了使用减少数量的处理步骤在公共基板上形成高压和低压晶体管的方法和装置。 一种示例性方法包括使用第一掩模和第一注入工艺同时注入在至少第一高电压晶体管阱和第一低电压晶体管阱上形成阱，所述公共衬底由隔离结构隔开，所述隔离结构将第一深度延伸到衬底中 第一导电类型的掺杂材料进入低压晶体管阱的沟道区域和用于高压晶体管阱的漏极区域。

公开(公告)号：US08710555B2

公开(公告)日：2014-04-29

申请号：US13417744

申请日：2012-03-12

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/06

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。

公开(公告)号：US07863152B2

公开(公告)日：2011-01-04

申请号：US12072445

申请日：2008-02-26

申请人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  Quan WangXiao ,  Hyun-min Choi

发明人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  Quan WangXiao ,  Hyun-min Choi

IPC分类号： H01L21/762

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

摘要翻译： 提供了具有应变层的半导体器件和制造具有能够减小负载效应的应变层的半导体器件的方法。 通过设置不重叠的活动假人和门虚拟物，可以确保将形成应变层虚拟物的活动虚拟物的面积，从而降低装载效果。

公开(公告)号：US07566937B2

公开(公告)日：2009-07-28

申请号：US11391377

申请日：2006-03-29

申请人： XiaoQuan Wang ,  Shigenobu Maeda ,  Min-Joo Kim

发明人： XiaoQuan Wang ,  Shigenobu Maeda ,  Min-Joo Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/4908

摘要： Disclosed is a MOS transistor including a multi-work function metal nitride gate electrode. The MOS transistor comprises a semiconductor substrate and a central gate electrode formed on the semiconductor substrate. The central gate electrode is formed of a metal nitride layer. A source side gate electrode and a drain side gate electrode are formed on respective opposite sidewalls of the central gate electrode. The source and drain side gate electrodes are composed of doped metal nitride containing first impurities having an electronegativity less than that of nitrogen or second impurities having an electronegativity greater than that of nitrogen.

摘要翻译： 公开了一种包括多功能金属氮化物栅电极的MOS晶体管。 MOS晶体管包括形成在半导体衬底上的半导体衬底和中心栅电极。 中心栅电极由金属氮化物层形成。 源极侧栅电极和漏极侧栅电极形成在中央栅电极的相对的相对侧壁上。 源极和漏极侧栅电极由掺杂的金属氮化物组成，掺杂的金属氮化物含有电负性小于氮的第一杂质或具有大于氮的电负性的第二杂质。

公开(公告)号：US20080150076A1

公开(公告)日：2008-06-26

申请号：US11951585

申请日：2007-12-06

申请人： Myung-Hee Nam ,  Shigenobu Maeda ,  Jae-Ho Lee

发明人： Myung-Hee Nam ,  Shigenobu Maeda ,  Jae-Ho Lee

IPC分类号： H01L27/00 ,  G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an electrical fuse, a semiconductor device having the same, and a method of programming and reading the electrical fuse. The electrical fuse includes first and second anodes disposed apart from each other. A cathode is interposed between the first and second anodes. A first fuse link couples the first anode to the cathode, and a second fuse link couples the second anode to the cathode.

摘要翻译： 提供一种电熔丝，具有该电熔丝的半导体器件，以及编程和读取该电熔丝的方法。 电熔丝包括彼此分开设置的第一和第二阳极。 阴极插在第一和第二阳极之间。 第一熔断体将第一阳极耦合到阴极，第二熔断体将第二阳极耦合到阴极。

公开(公告)号：US20080117011A1

公开(公告)日：2008-05-22

申请号：US12021494

申请日：2008-01-29

申请人： Shigenobu Maeda ,  Jeong-hwan Yang

发明人： Shigenobu Maeda ,  Jeong-hwan Yang

IPC分类号： H01F17/00 ,  H01F5/00

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip inductor can include an outer inductor portion that separates an inner region of the inductor from an outer region of the inductor outside the inductor. An interconnect inductor portion is electrically coupled to the main inductor portion wherein the interconnect inductor portion can include extension portions that follow the contour of the adjacent portions of the outer inductor in the inner region of the inductor. An input path is coupled to the outer inductor portion through the extension portion and extends away from the inductor beneath the outer inductor portion on a first side thereof. An output path is coupled to the outer inductor portion through the extension portion and extends away from the inductor beneath the outer inductor portion on a second side of the inductor opposite the first side.

摘要翻译： 片上电感器可以包括外部电感器部分，其将电感器的内部区域与电感器外部的电感器的外部区域分开。 互连电感器部分电耦合到主电感器部分，其中互连电感器部分可以包括在电感器的内部区域中跟随外部电感器的相邻部分的轮廓的延伸部分。 输入路径通过延伸部分耦合到外部电感器部分，并且在外部电感器部分的第一侧上远离电感器延伸。 输出路径通过延伸部分耦合到外部电感器部分，并且在电感器的与第一侧相对的第二侧上远离电感器下方的电感器延伸。