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    DISTRIBUTED SYSTEM GENERATING RULE COMPILER ENGINE APPARATUSES, METHODS, SYSTEMS AND MEDIA
    42.
    发明申请
    DISTRIBUTED SYSTEM GENERATING RULE COMPILER ENGINE APPARATUSES, METHODS, SYSTEMS AND MEDIA 审中-公开

    公开(公告)号：US20200293916A1

    公开(公告)日：2020-09-17

    申请号：US16816367

    申请日：2020-03-12

    申请人： Yadong Li

    发明人： Yadong Li

    IPC分类号： G06N5/02 ,  H04L29/08

    摘要： An output rule specified via a distributed system execution request data structure for a requested calculation is determined, and a current rule is initialized to the output rule. A rule lookup table data structure is queried to determine a set of matching rules, corresponding to the current rule. The best matching rule is selected. A logical dependency graph (LDG) data structure is generated by adding LDG nodes and LDG edges corresponding to the best matching rule, precedent rules of the best matching rule, and precedent rules of each precedent rule. An execution complexity gauge value and a set of distributed worker processes are determined. The LDG data structure is divided into a set of subgraphs. Each worker process is initialized with the subgraph assigned to it. Execution of the requested calculation is coordinated and a computation result of the LDG node corresponding to the output rule is obtained.

    FLOW DIRECTOR-BASED LOW LATENCY NETWORKING
    44.
    发明申请
    FLOW DIRECTOR-BASED LOW LATENCY NETWORKING 有权
    基于流程总监的低期限网络

    公开(公告)号：US20140280709A1

    公开(公告)日：2014-09-18

    申请号：US13836959

    申请日：2013-03-15

    申请人： Yadong Li ,  Anvil Vasudevan ,  Linden Cornett

    发明人： Yadong Li ,  Anvil Vasudevan ,  Linden Cornett

    IPC分类号： H04L29/08

    CPC分类号： H04L67/10 ,  G06F13/385

    摘要： Generally, this disclosure relates to low latency networking. A system may include processor circuitry comprising at least one processor; memory circuitry configured to store an application, a receive queue and a networking stack comprising a network device driver; a network controller comprising a flow director, the network controller configured to couple the host device to at least one link partner and the flow director configured to store one or more selected received packets in the receive queue, the selecting based, at least in part, on a packet flow identifier; and a network device driver configured to identify the receive queue in response to a polling request comprising the packet flow identifier; poll the receive queue; and process each received packet stored in the receive queue.

    摘要翻译： 通常，本公开涉及低延迟网络。 系统可以包括包括至少一个处理器的处理器电路; 存储器电路，被配置为存储应用，接收队列和包括网络设备驱动器的网络堆栈; 网络控制器，其包括流导向器，所述网络控制器被配置为将主机设备耦合到至少一个链路伙伴，并且所述流导向器被配置为在接收队列中存储一个或多个所选择的接收分组，所述选择至少部分地基于， 对数据包流标识符; 以及网络设备驱动器，被配置为响应于包括所述分组流标识符的轮询请求来识别所述接收队列; 轮询接收队列; 并处理存储在接收队列中的每个接收到的分组。

    NUMA-AWARE SCALING FOR NETWORK DEVICES
    45.
    发明申请
    NUMA-AWARE SCALING FOR NETWORK DEVICES 审中-公开
    用于网络设备的NUMA-AWARE SCALING

    公开(公告)号：US20130326000A1

    公开(公告)日：2013-12-05

    申请号：US13895917

    申请日：2013-05-16

    申请人： Yadong Li

    发明人： Yadong Li

    IPC分类号： G06F15/173

    CPC分类号： G06F15/17331 ,  H04L45/00 ,  H04L49/9036

    摘要： The present disclosure describes a method and apparatus for network traffic processing in a non-uniform memory access architecture system. The method includes allocating a Tx/Rx Queue pair for a node, the Tx/Rx Queue pair allocated in a local memory of the node. The method further includes routing network traffic to the allocated Tx/Rx Queue pair. The method may include designating a core in the node for network traffic processing. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开描述了用于非均匀存储器访问架构系统中的网络流量处理的方法和装置。 该方法包括为节点分配Tx / Rx队列对，Tx / Rx队列对分配在该节点的本地存储器中。 该方法还包括将网络业务路由到所分配的Tx / Rx队列对。 该方法可以包括指定节点中的核心用于网络流量处理。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Method and apparatus for improving the efficiency of interrupt delivery at runtime in a network system
    47.
    发明授权
    Method and apparatus for improving the efficiency of interrupt delivery at runtime in a network system 有权
    一种提高网络系统运行时中断传输效率的方法和装置

    公开(公告)号：US08296490B2

    公开(公告)日：2012-10-23

    申请号：US11771209

    申请日：2007-06-29

    申请人： Yadong Li ,  Sujoy Sen

    发明人： Yadong Li ,  Sujoy Sen

    IPC分类号： G06F13/24 ,  G06F15/16 ,  G06F3/00

    CPC分类号： G06F9/3861 ,  G06F13/24 ,  H04L49/90

    摘要： Processor affinity of an application/thread may be used to deliver an interrupt caused by the application/thread to a best processor at runtime. The processor to which the interrupt is delivered may either run the target application/thread or be located in the same socket as the processor that runs the target application/thread. The processor affinity of the application/thread may be pushed down at runtime to a network device, a chipset, a memory control hub (“MCH”), or an input/output hub (“IOH”), which will facilitate delivery of the interrupt using that affinity information.

    摘要翻译： 应用程序/线程的处理器亲和性可能用于在运行时将由应用程序/线程引起的中断传递到最佳处理器。 发送中断的处理器可以运行目标应用程序/线程，也可以位于与运行目标应用程序/线程的处理器相同的套接字中。 应用程序/线程的处理器亲和性可能在运行时被推下到网络设备，芯片组，存储器控制集线器（MCH）或输入/输出集线器（IOH），这将有助于使用该亲和力传送中断 信息。

    TRAFFIC CLASS BASED ADAPTIVE INTERRUPT MODERATION
    48.
    发明申请
    TRAFFIC CLASS BASED ADAPTIVE INTERRUPT MODERATION 有权
    基于交通类的自适应中断调制

    公开(公告)号：US20120254492A1

    公开(公告)日：2012-10-04

    申请号：US13076789

    申请日：2011-03-31

    申请人： Yadong Li ,  Linden Cornett

    发明人： Yadong Li ,  Linden Cornett

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： An apparatus which comprises two or more moderation timers associated with an interrupt vector is presented. In one embodiment, the apparatus comprises two or more interrupt vectors and moderation timers are set with different interrupt rates. An interrupt vector logic unit sends an interrupt vector if there is an interrupt event from the queue associated with a moderation timer and the moderation timer expires.

    摘要翻译： 提出了一种包括与中断向量相关联的两个或更多个调节定时器的装置。 在一个实施例中，该装置包括两个或多个中断向量，并且以不同的中断速率设置调节定时器。 中断向量逻辑单元发送一个中断向量，如果存在与调节定时器相关联的队列中断事件，并且调节定时器到期。

    HASHING PACKET CONTENTS TO DETERMINE A PROCESSOR
    49.
    发明申请
    HASHING PACKET CONTENTS TO DETERMINE A PROCESSOR 审中-公开
    散装包内容以确定处理器

    公开(公告)号：US20110142050A1

    公开(公告)日：2011-06-16

    申请号：US13031368

    申请日：2011-02-21

    申请人： Yadong Li ,  Xinan Tang

    发明人： Yadong Li ,  Xinan Tang

    IPC分类号： H04L12/56

    CPC分类号： H04L69/16 ,  H04L69/161 ,  H04L69/163 ,  H04L69/22

    摘要： The disclosure includes a description of an apparatus having circuitry to determine a first hash value for a first packet tuple of a first packet traveling in a first direction of a duplex connection and determine a processor for the first packet from a set of multiple processors based, at least in part, on the first hash value. The apparatus includes circuitry to determine a second hash value for a second packet tuple of a second packet traveling in a second direction of the duplex connection and determine the same processor for the second packet from the set of multiple processors based, at least in part, on the second hash value.

    摘要翻译： 本公开包括具有电路的描述，该电路具有确定在双工连接的第一方向上行进的第一分组的第一分组元组的第一散列值，并且从一组多个处理器确定第一分组的处理器， 至少部分地基于第一个哈希值。 该装置包括用于确定在双工连接的第二方向上行进的第二分组的第二分组元组的第二哈希值的电路，并且至少部分地基于多个处理器的集合来确定用于第二分组的相同处理器， 在第二个哈希值上。