公开(公告)号：US06674126B2

公开(公告)日：2004-01-06

申请号：US10073671

申请日：2002-02-11

申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： A01L29772

CPC分类号： H01L29/7802 ,  H01L29/0634

摘要： A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

摘要翻译： 半导体器件有助于在漏极漂移区周围的半导体芯片的部分中获得更高的击穿电压并且提高其雪崩耐受能力。 根据本发明的垂直MOSFET包括漏极层; 漏极层上的漏极漂移区，包括第一交替导电型层的漏极漂移区; 在漏极层和漏极漂移区域周围的击穿耐受区域（半导体芯片的外围区域），在MOSFET的导通状态基本上不提供电流路径的击穿承受区域，击穿耐受区域在断开状态 MOSFET，包括第二交替导电类型层的击穿耐受区域和栅极焊盘下方的下部区域，以及包括第三交变导电类型层的下部区域。

公开(公告)号：US06611021B1

公开(公告)日：2003-08-26

申请号：US09693574

申请日：2000-10-20

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Susumu Iwamoto ,  Takahiro Sato

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Susumu Iwamoto ,  Takahiro Sato

IPC分类号： H01L2994

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66712

摘要： A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the semiconductor device. The vertical MOSFET according to the invention includes an alternating-conductivity-type drain drift layer on an n+-type drain layer as a substrate. The alternating-conductivity-type drain drift layer is formed of n-type drift current path regions and p-type partition regions alternately arranged laterally with each other. The n-type drift current path regions and p-type partition regions extend in perpendicular to n+-type drain layer. Each p-type partition region is formed by vertically connecting p-type buried diffusion unit regions Up. The n-type drift current path regions are residual regions, left after connecting p-type buried diffusion unit regions Up, with the conductivity type thereof unchanged. The alternating-conductivity-type drain drift layer is formed by repeating the step of epitaxial layer growth and the step of implanting p-type impurity ions and by diffusing the impurity ions at once from the impurity sources located on multiple levels.

摘要翻译： 半导体器件包括易于制造的交替导电类型的改进的漏极漂移层结构，并且有助于实现高电流容量和高击穿电压，并提供制造半导体器件的方法。 根据本发明的垂直MOSFET包括作为衬底的n +型漏极层上的交替导电型漏极漂移层。 交流导电型漏极漂移层由n型漂移电流路径区域和彼此交替布置的p型分隔区域形成。 n型漂移电流路径区域和p型分隔区域垂直于n +型漏极层延伸。 每个p型分隔区域通过垂直连接p型埋入扩散单元区域Up而形成。 n型漂移电流路径区域是在连接p型埋入扩散单元区域Up之后剩余的区域，其导电类型不变。 交替导电型漏极漂移层是通过重复外延层生长的步骤和注入p型杂质离子的步骤和通过从位于多个层上的杂质源一次扩散杂质离子而形成的。

公开(公告)号：US6133661A

公开(公告)日：2000-10-17

申请号：US187469

申请日：1998-11-06

申请人： Yoshinao Okawa ,  Yoshihiro Murano ,  Isao Ito ,  Kenichi Okada ,  Kazuo Funabashi ,  Masanori Miyamoto ,  Kiyohito Mizuide ,  Yasuhiko Onishi ,  Masaaki Hoko ,  Hirotugu Kinoshita ,  Fumihiro Itano ,  Makoto Noda ,  Takeshi Uesugi ,  Kiyoshi Nagasawa ,  Shuzo Tanigaki ,  Yoshiyuki Ema

发明人： Yoshinao Okawa ,  Yoshihiro Murano ,  Isao Ito ,  Kenichi Okada ,  Kazuo Funabashi ,  Masanori Miyamoto ,  Kiyohito Mizuide ,  Yasuhiko Onishi ,  Masaaki Hoko ,  Hirotugu Kinoshita ,  Fumihiro Itano ,  Makoto Noda ,  Takeshi Uesugi ,  Kiyoshi Nagasawa ,  Shuzo Tanigaki ,  Yoshiyuki Ema

IPC分类号： C08G73/18 ,  H01B3/30 ,  H01B7/28 ,  H02K3/30 ,  H02K3/50 ,  H02K5/15 ,  H02K7/08 ,  H02K9/06 ,  H02K5/08

CPC分类号： H02K5/15 ,  C08G73/18 ,  H01B3/303 ,  H02K3/30 ,  H02K7/083 ,  H02K3/50 ,  H02K9/06

摘要： The invention relates to a rotating electric machine including a coil of a wire having thereon an insulating coating comprising a polybenzimidazole. This rotating electric machine is stably maintained for a long time in dielectric strength even under a highly radioactive environment, due to the use of the special insulating coating. With this, the rotating electric machine can be driven stably for a long time. The invention further relates to another rotating electric machine including (a) a rotor having a rotating shaft; (b) a bearing for supporting the rotating shaft; and (c) a grease applied to the bearing. This grease contains (1) a polyphenyl ether having at least three aromatic rings in the molecule and (2) a urea. The rotor of this rotating electric machine is stably supported in the bearing for a long time even under a highly radioactive environment, due to the use of the special grease. Thus, this rotating electric machine can also be rotated stably for a long time.

摘要翻译： 本发明涉及一种旋转电机，其包括其上具有包含聚苯并咪唑的绝缘涂层的线圈。 由于使用了特殊的绝缘涂层，该旋转电机即使在放射性高的环境下也能够长时间地保持介电强度。 由此，可以长时间稳定地驱动旋转电机。 本发明还涉及另一种旋转电机，其包括：（a）具有旋转轴的转子; （b）用于支撑旋转轴的轴承; 和（c）施加到轴承上的润滑脂。 该润滑脂包含（1）在分子中具有至少三个芳环的聚苯醚和（2）尿素。 这种旋转电机的转子由于使用了特殊的润滑脂，即使在高度放射性的环境下也可以长期稳定地支撑在轴承中。 因此，该旋转电机也可以长时间稳定地旋转。

公开(公告)号：US4808709A

公开(公告)日：1989-02-28

申请号：US895925

申请日：1986-08-13

申请人： Yasuhiko Onishi

发明人： Yasuhiko Onishi

IPC分类号： A61L27/16 ,  C08F251/00 ,  G02B1/04 ,  C07G7/00 ,  C08B37/02 ,  C08F16/38 ,  G02C7/04

CPC分类号： C08B37/0021 ,  A61F2/16 ,  A61L27/16 ,  C08F251/00 ,  G02B1/04 ,  G02C7/04

摘要： A cationic dextran compound matrix-copolymer obtained by reacting with a polymerizable unsaturated acid or a polymerizable unsaturated acid and olefin compound a dextran derivative which is introduced cationic radicals thereinto. It is highly hydrophilic and a material having a high affinity for a living body and which is, therefore, useful for making contact lenses, intraocular lenses, artificial bones and blood vessels, etc.

摘要翻译： 通过与可聚合不饱和酸或可聚合不饱和酸和烯烃化合物反应引入阳离子基团的葡聚糖衍生物得到的阳离子葡聚糖复合基质共聚物。 它是高亲水性的，对生物体具有高亲和力的材料，因此可用于制造隐形眼镜，人工晶状体，人造骨和血管等。

公开(公告)号：US08786015B2

公开(公告)日：2014-07-22

申请号：US13369413

申请日：2012-02-09

申请人： Takahiro Tamura ,  Yasuhiko Onishi

发明人： Takahiro Tamura ,  Yasuhiko Onishi

IPC分类号： H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/0696 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7815

摘要： A super-junction semiconductor device includes a drift layer including an alternating-conductivity-type layer that includes n-type region and p-type region arranged alternately in parallel to the first major surface of an n-type substrate. These alternating regions extend deep in a direction perpendicular to the first major surface. The first major surface includes a main device region with a gate electrode and a main source electrode and sensing device region with a gate electrode and a sensing source electrode. There is a common drain electrode on the second major surface of the substrate. There is a separation region between the main device region and the sensing device region. It includes an n-type region and p-type regions in the n-type region. The p-type regions are in an electrically floating state in the directions parallel and perpendicular to the first alternating-conductivity-type layer.

摘要翻译： 超结半导体器件包括包括交替导电型层的漂移层，该交替导电型层包括与n型衬底的第一主表面交替平行排列的n型区域和p型区域。 这些交替区域在垂直于第一主表面的方向上深度延伸。 第一主表面包括具有栅电极和主源电极的主器件区域和具有栅电极和感测源电极的感测器件区域。 在基板的第二主表面上有一个共同的漏电极。 在主设备区域和感测设备区域之间存在分离区域。 它包括n型区域和n型区域中的p型区域。 p型区域在与第一交变导电型层平行且垂直的方向上处于电浮置状态。

公开(公告)号：US08432013B2

公开(公告)日：2013-04-30

申请号：US13019359

申请日：2011-02-02

申请人： Yasuhiko Onishi

发明人： Yasuhiko Onishi

IPC分类号： H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611

摘要： A semiconductor device is provided with a peripheral region that has a narrow width and exhibits good electric field relaxation and high robustness against induced charges. The device has an active region for main current flow and a peripheral region surrounding the active region on a principal surface of a semiconductor substrate of a first conductivity type. The peripheral region has a guard ring of a second conductivity type composed of straight sections and curved sections connecting the straight sections formed in a region of the principal surface surrounding the active region, and a pair of polysilicon field plates in a ring shape formed separately on inner and outer circumferential sides of the guard ring. The surface of the guard ring and the pair of polysilicon field plates of the inner circumferential side and the outer circumferential side are electrically connected with a metal film in the curved section.

摘要翻译： 半导体器件设置有具有窄宽度并且表现出良好的电场弛豫和对诱导电荷的高鲁棒性的外围区域。 该器件具有用于主电流的有源区和围绕第一导电类型的半导体衬底的主表面上的有源区的周边区。 周边区域具有由直线部分构成的第二导电类型的保护环和连接形成在有源区周围的主表面的区域中的直线部分的弯曲部分，以及分别形成为环状的一对多晶硅场板 保护环的内周侧和外周侧。 保护环的表面和内周侧和外周侧的一对多晶硅场板与弯曲部中的金属膜电连接。

公开(公告)号：US06903418B2

公开(公告)日：2005-06-07

申请号：US10678941

申请日：2003-10-03

申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/772

CPC分类号： H01L29/7802 ,  H01L29/0634

摘要： A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

摘要翻译： 半导体器件有助于在漏极漂移区周围的半导体芯片的部分中获得更高的击穿电压并且提高其雪崩耐受能力。 根据本发明的垂直MOSFET包括漏极层; 漏极层上的漏极漂移区，包括第一交替导电型层的漏极漂移区; 在漏极层和漏极漂移区域周围的击穿耐受区域（半导体芯片的外围区域），在MOSFET的导通状态基本上不提供电流路径的击穿承受区域，击穿耐受区域在断开状态 MOSFET，包括第二交替导电类型层的击穿耐受区域和栅极焊盘下方的下部区域，以及包括第三交变导电类型层的下部区域。

公开(公告)号：US06900109B2

公开(公告)日：2005-05-31

申请号：US10376662

申请日：2003-02-28

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Susumu Iwamoto ,  Takahiro Sato

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Susumu Iwamoto ,  Takahiro Sato

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/76

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66712

摘要： A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the semiconductor device. The vertical MOSFET according to the invention includes an alternating-conductivity-type drain drift layer on an n+-type drain layer as a substrate. The alternating-conductivity-type drain drift layer is formed of n-type drift current path regions and p-type partition regions alternately arranged laterally with each other. The n-type drift current path regions and p-type partition regions extend in perpendicular to n+-type drain layer. Each p-type partition region is formed by vertically connecting p-type buried diffusion unit regions Up. The n-type drift current path regions are residual regions, left after connecting p-type buried diffusion unit regions Up, with the conductivity type thereof unchanged. The alternating-conductivity-type drain drift layer is formed by repeating the step of epitaxial layer growth and the step of implanting p-type impurity ions and by diffusing the impurity ions at once from the impurity sources located on multiple levels.

摘要翻译： 半导体器件包括易于制造的交替导电类型的改进的漏极漂移层结构，并且有助于实现高电流容量和高击穿电压，并提供制造半导体器件的方法。 根据本发明的垂直MOSFET包括作为衬底的n + +型漏极层上的交替导电型漏极漂移层。 交流导电型漏极漂移层由n型漂移电流路径区域和彼此交替布置的p型分隔区域形成。 n型漂移电流路径区域和p型隔离区域垂直于n + +型漏极层延伸。 每个p型分隔区域通过垂直连接p型掩埋扩散单元区域U P而形成。 n型漂移电流路径区域是在连接p型掩埋扩散单元区域U P1之后剩余的区域，导电类型不变。 交替导电型漏极漂移层是通过重复外延层生长的步骤和注入p型杂质离子的步骤和通过从位于多个层上的杂质源一次扩散杂质离子而形成的。

公开(公告)号：US20050017292A1

公开(公告)日：2005-01-27

申请号：US10925407

申请日：2004-08-25

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/06 ,  H01L21/331 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

公开(公告)号：US06696728B2

公开(公告)日：2004-02-24

申请号：US10099449

申请日：2002-03-15

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/7395 ,  H01L29/872

摘要： To provide a super-junction MOSFET reducing the tradeoff relation between the on-resistance and the breakdown voltage greatly and having a peripheral structure, which facilitates reducing the leakage current in the OFF-state thereof and stabilizing the breakdown voltage thereof. The vertical MOSFET according to the invention includes a drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (peripheral region) including a second alternating conductivity type layer around drain drift region, second alternating conductivity type layer being formed of layer-shaped vertically-extending n-type regions and layer-shaped vertically-extending p-type regions laminated alternately; an n-type region around second alternating conductivity type layer; and a p-type region formed in the surface portion of n-type region to reduce the leakage current in the OFF-state of the MOSFET.

摘要翻译： 为了提供一种超级结MOSFET，大大降低了导通电阻和击穿电压之间的折衷关系，并具有外围结构，这有助于减小其截止状态下的漏电流并稳定其击穿电压。 根据本发明的垂直MOSFET包括包括第一交变导电类型层的漏极漂移区; 包括漏极漂移区周围的第二交变导电型层的击穿耐受区域（周边区域），层叠的上下方向延伸的n型区域形成的第二交替导电型层和层叠的上下方向延伸的p型区域 交替; 围绕第二交变导电类型层的n型区域; 以及形成在n型区域的表面部分中的p型区域，以减小MOSFET的截止状态下的漏电流。