公开(公告)号：US20090015743A1

公开(公告)日：2009-01-15

申请号：US12168185

申请日：2008-07-07

申请人： Hisashi Ohtani ,  Yasushi Ogata ,  Yoshiharu Hirakata

发明人： Hisashi Ohtani ,  Yasushi Ogata ,  Yoshiharu Hirakata

IPC分类号： G02F1/136

CPC分类号： H01L27/12 ,  G02F1/136209 ,  G02F1/136213 ,  H01L27/1255 ,  H01L27/13

摘要： An conductive coating serves as a light shield film and is kept at a given voltage. A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between the conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer film serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching. According to another aspect of the invention, the conductive coating has a portion that is in contact with the lower insulating layer in a region where the conductive coating coextends with the metal interconnection.

摘要翻译： 导电涂层用作遮光膜并保持在给定的电压。 金属互连位于与源极线相同的层中，并连接到薄膜晶体管的漏极。 层间绝缘膜由至少下绝缘层和上绝缘层构成，并形成在导电涂层和源极线之间。 根据本发明的一个方面，通过金属互连和用作两个电极的导电涂层和至少用作电介质的下绝缘层膜形成辅助电容器。 辅助电容器形成在通过蚀刻去除上绝缘层的层间绝缘膜的区域中。 根据本发明的另一方面，导电涂层具有在导电涂层与金属互连共同延伸的区域中与下绝缘层接触的部分。

公开(公告)号：US20090001896A1

公开(公告)日：2009-01-01

申请号：US12055432

申请日：2008-03-26

申请人： Shunpei Yamazaki ,  Masakazu Murakami ,  Naomi Kawakami ,  Hisashi Ohtani

发明人： Shunpei Yamazaki ,  Masakazu Murakami ,  Naomi Kawakami ,  Hisashi Ohtani

IPC分类号： G09G3/30

CPC分类号： H01L27/3244 ,  H01L51/001 ,  H01L51/0037 ,  H01L51/5203 ,  H01L51/56 ,  H01L2251/5315

摘要： The inventors has been anticipated that there is no problem in employing electron gun deposition as a method of forming a metallic layer on the EL layer because the TFT is disposed blow the ET layer in the active matrix light-emitting device. However, since the TFT is extremely sensitive to ionized evaporated particles, the secondary electron, the reflecting electron, and so on generated by the electron gun, little damage was observed on the EL layer, but significant damages were found on the TFT when electron gun deposition is employed. The invention provides an active matrix light-emitting device having superior TFT characteristics (ON current, OFF to current, Vth, S-value, and so on), in which an organic compound layer and a metallic layer (cathode or anode) are formed by means of resistive heating having least influence to the TFT.

摘要翻译： 本发明人已经预期使用电子枪沉积作为在EL层上形成金属层的方法是没有问题的，因为TFT被置于有源矩阵发光器件中吹扫ET层。 然而，由于TFT对电离蒸发颗粒非常敏感，所以由电子枪产生的二次电子，反射电子等在EL层上观察到很小的损伤，但是当电子枪 使用沉积。 本发明提供一种具有优异的TFT特性（导通电流，截止电流，Vth，S值等）的有源矩阵发光器件，其中形成有机化合物层和金属层（阴极或阳极） 通过对TFT具有最小影响的电阻加热。

公开(公告)号：US20080308830A1

公开(公告)日：2008-12-18

申请号：US12179615

申请日：2008-07-25

申请人： Shunpei Yamazaki ,  Hisashi Ohtani ,  Toshiji Hamatani

发明人： Shunpei Yamazaki ,  Hisashi Ohtani ,  Toshiji Hamatani

IPC分类号： H01L33/00

CPC分类号： H01L27/3244 ,  G02F1/13454 ,  H01L27/12 ,  H01L27/1277 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78645 ,  H01L51/5246 ,  H01L51/5284 ,  H01L2029/7863 ,  H01L2251/5315

摘要： An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.

摘要翻译： NTFT的有源层包括沟道形成区，至少第一杂质区，至少第二杂质区和至少第三杂质区。 随着与沟道形成区域的距离变长，第一，第二和第三杂质区域中的杂质浓度增加。 第一杂质区形成为与侧壁重叠。 可以通过侧壁起电极的作用来实现栅极重叠结构。

公开(公告)号：US20080300044A1

公开(公告)日：2008-12-04

申请号：US12153645

申请日：2008-05-22

申请人： Hisashi Ohtani

发明人： Hisashi Ohtani

IPC分类号： A63F9/24

CPC分类号： G07F17/3241 ,  G07F17/32 ,  G07F17/3202 ,  G07F17/3293

摘要： An object is to provide a card game machine capable of enhancing gameplay. A card game machine has a game board including a plurality of reader/writers configured to communicate with a semiconductor device which is mounted on a card and capable of wireless communication, and a control device connected to the reader/writer and configured to determine the position or orientation of the card or whether the card is put face up or down based on a signal from the reader/writer. By arrangement of a plurality of reader/writers and RF chips in the game board, not only data of the card but also signal strength can be detected, and the detailed position of an RF chip of the card which is placed on the game board can be specified.

摘要翻译： 目的是提供一种能够增强游戏玩法的纸牌游戏机。 一种纸牌游戏机具有：游戏板，包括被配置为与安装在卡上并能够进行无线通信的半导体装置进行通信的多个读取器/写入器;以及连接到读取器/写入器并被配置为确定位置的控制装置 基于来自读写器的信号，卡或卡的取向或者卡是面朝上还是向下放置。 通过在游戏板中配置多个读取器/写入器和RF芯片，不仅可以检测卡的数据，还可以检测信号强度，并且放置在游戏板上的卡的RF芯片的详细位置可以 被指定。

公开(公告)号：US07446340B2

公开(公告)日：2008-11-04

申请号：US11890340

申请日：2007-08-06

申请人： Hisashi Ohtani

发明人： Hisashi Ohtani

IPC分类号： H01L29/04

CPC分类号： H01L33/16 ,  G02B5/30 ,  G02B27/017 ,  G02B27/0172 ,  G02B2027/0178 ,  G02F2001/13625 ,  G09G3/3225 ,  H01L27/12 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.

摘要翻译： 本发明的目的是在顶栅型TFT中形成具有高精度的低浓度杂质区。 通过使用由导电膜形成的图案作为掩模将磷添加到半导体层中，以自对准方式形成N型杂质区。 将正性光致抗蚀剂施加到基板上以覆盖图案，然后暴露于施加到基板背面的光，然后显影，由此形成光致抗蚀剂110。 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻图案以形成栅电极。 通过使用栅极作为掺杂掩模，以自对准的方式在半导体层中形成沟道形成区域，源极区域，漏极区域和低浓度杂质区域。

公开(公告)号：US20080113488A1

公开(公告)日：2008-05-15

申请号：US11926573

申请日：2007-10-29

申请人： Shunpei Yamazaki ,  Hisashi Ohtani

发明人： Shunpei Yamazaki ,  Hisashi Ohtani

IPC分类号： H01L21/30

CPC分类号： H01L27/1266 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/78603 ,  Y10S438/973 ,  Y10S438/977

摘要： A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

公开(公告)号：US20080054269A1

公开(公告)日：2008-03-06

申请号：US11926598

申请日：2007-10-29

申请人： Shunpei Yamazaki ,  Hisashi Ohtani

发明人： Shunpei Yamazaki ,  Hisashi Ohtani

IPC分类号： H01L29/04

CPC分类号： H01L27/1266 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/78603 ,  Y10S438/973 ,  Y10S438/977

摘要： A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

公开(公告)号：US07339235B1

公开(公告)日：2008-03-04

申请号：US09635832

申请日：2000-08-09

申请人： Shunpei Yamazaki ,  Hisashi Ohtani ,  Jun Koyama ,  Takeshi Fukunaga

发明人： Shunpei Yamazaki ,  Hisashi Ohtani ,  Jun Koyama ,  Takeshi Fukunaga

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1041 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78654

摘要： A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel direction. The impurity regions 104 are effective in suppressing the short channel effects. More specifically, the impurity regions 104 suppress expansion of a drain-side depletion layer, so that the punch-through phenomenon can be prevented. Further, the impurity regions cause a narrow channel effect, so that reduction in threshold voltage can be lessened.

摘要翻译： 具有短通道长度同时抑制短通道效应的精细半导体器件。 在通道形成区域103中形成线状图案或点图案化的杂质区域104，以使其大致平行于沟道方向。 杂质区域104有效地抑制短路效应。 更具体地，杂质区域104抑制漏极侧耗尽层的膨胀，从而可以防止穿通现象。 此外，杂质区域引起窄通道效应，从而可以减小阈值电压的降低。

公开(公告)号：US07326604B2

公开(公告)日：2008-02-05

申请号：US10765952

申请日：2004-01-29

申请人： Shunpei Yamazaki ,  Hisashi Ohtani ,  Akiharu Miyanaga ,  Toru Mitsuki ,  Takeshi Fukunaga

发明人： Shunpei Yamazaki ,  Hisashi Ohtani ,  Akiharu Miyanaga ,  Toru Mitsuki ,  Takeshi Fukunaga

IPC分类号： H01L21/84

CPC分类号： H01L27/1222 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/78609 ,  H01L29/78675 ,  H01L29/78696

摘要： In a semiconductor device using a crystalline semiconductor film on a substrate 106 having an insulating surface, impurities are locally implanted into an active region 102 to form a pinning region 104. The pinning region 104 suppresses the spread of a depletion layer from the drain side to effectively prevent the short channel effect. Also, since a channel forming region 105 is intrinsic or substantially intrinsic, a high mobility is realized.

摘要翻译： 在具有绝缘表面的衬底106上使用结晶半导体膜的半导体器件中，将杂质局部注入到有源区102中以形成钉扎区104。 钉扎区域104抑制耗尽层从漏极侧的扩展，以有效地防止短沟道效应。 此外，由于沟道形成区域105是固有的或基本上固有的，因此实现高迁移率。

公开(公告)号：US07307007B2

公开(公告)日：2007-12-11

申请号：US11393764

申请日：2006-03-31

申请人： Shunpei Yamazaki ,  Akiharu Miyanaga ,  Toru Mitsuki ,  Hisashi Ohtani

发明人： Shunpei Yamazaki ,  Akiharu Miyanaga ,  Toru Mitsuki ,  Hisashi Ohtani

IPC分类号： H01L21/20

CPC分类号： H01L29/78603 ,  H01L21/02532 ,  H01L21/02672 ,  H01L21/3226 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1277 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78621

摘要： An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 μm or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

摘要翻译： 用于制造下绝缘层104的绝缘膜103形成在石英或半导体衬底100上。 在绝缘膜103的表面上形成与基板100的凹部101a〜101d对应的凹部105a〜105d。 该绝缘膜103的表面被平坦化以形成下绝缘层104。 通过该平坦化处理，距离L 1，L 2，... 。 。 在下绝缘层104的凹部106a，106b，106d之间的Ln为0.3μm以上，各凹部的深度为10nm以下。 下绝缘膜104的表面的均方根表面粗糙度为0.3nm以下。 由此，在凹部106a，106b，106d中，可以避免阻挡半导体薄膜的晶体生长，并且晶粒边界可以基本消失。