公开(公告)号：US07312110B2

公开(公告)日：2007-12-25

申请号：US11098648

申请日：2005-04-04

申请人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

发明人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

IPC分类号： H01L21/00

CPC分类号： H01L27/1108 ,  H01L27/0688 ,  H01L27/11 ,  H01L29/78603

摘要： Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

摘要翻译： 提供制造半导体器件的方法。 层间绝缘层设置在单晶半导体衬底上。 提供延伸穿过层间绝缘层的单晶半导体插头，并且在半导体衬底和单晶半导体插头上设置成型层图案。 模制层图案限定其中的开口，其至少部分地暴露单晶半导体插塞的一部分。 使用选择性外延生长技术在单晶半导体插塞的暴露部分上提供单晶半导体外延图案，其使用单晶半导体插塞的暴露部分作为籽晶层。 在开口中设置单晶半导体区域。 单晶半导体区域包括单晶半导体外延图案的至少一部分。

公开(公告)号：US20070128789A1

公开(公告)日：2007-06-07

申请号：US11673198

申请日：2007-02-09

申请人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho

发明人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho

IPC分类号： H01L21/8238

CPC分类号： H01L21/823481 ,  H01L21/823418

摘要： Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.

摘要翻译： 提供制造半导体器件的半导体器件和方法，其包括限定衬底的有源区的衬底中的衬底和器件隔离层。 器件隔离层具有垂直突出部分，其具有垂直延伸超出衬底表面的侧壁。 在有源区中的衬底的表面上提供外延层并延伸到器件隔离层上。 外延层与器件隔离层的垂直突出部分的侧壁间隔开。 在外延层上提供栅极图案，并且在栅极图案的相对侧的外延层中设置源极/漏极区域。

公开(公告)号：US20070042554A1

公开(公告)日：2007-02-22

申请号：US11589618

申请日：2006-10-30

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

IPC分类号： H01L21/336

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

摘要翻译： 提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和方法消除了由于具有垂直堆叠的上下栅极图案的SRAM单元的结构特性而产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。 在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。 下部有源区域具有两个较低的单元栅极图案。 主体图案与半导体衬底平行设置。 形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。 着陆垫设置在下单元栅极图案之间。 形成节点图案以同时接触上单元格栅图案和下单元栅格图案。

公开(公告)号：US07135746B2

公开(公告)日：2006-11-14

申请号：US11268138

申请日：2005-11-07

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

公开(公告)号：US20060102959A1

公开(公告)日：2006-05-18

申请号：US11280045

申请日：2005-11-15

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim ,  Kun-Ho Kwak ,  Hoon Lim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim ,  Kun-Ho Kwak ,  Hoon Lim

IPC分类号： H01L29/94

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern is provided on the interlayer insulating layer. The single crystalline semiconductor body pattern has an elevated region and contacts the single crystalline semiconductor plug. The method of forming the single crystalline semiconductor body pattern having the elevated region includes forming a sacrificial layer pattern covering the single crystalline semiconductor plug on the interlayer insulating layer. A capping layer is formed to cover the sacrificial layer pattern and the interlayer insulating layer, and the capping layer is patterned to form an opening which exposes a portion of the sacrificial layer pattern. Subsequently, the sacrificial layer pattern is selectively removed to form a cavity in the capping layer, and a planarized single crystalline semiconductor body pattern is formed to fill the cavity and the opening.

摘要翻译： 提供具有单晶薄膜晶体管的半导体集成电路器件及其制造方法。 半导体集成电路器件包括形成在半导体衬底上的层间绝缘层和贯穿层间绝缘层的单晶半导体插件。 在层间绝缘层上设置单晶体半导体图案。 单晶半导体主体图案具有升高的区域并与单晶半导体插头接触。 形成具有升高区域的单晶半导体主体图案的方法包括在层间绝缘层上形成覆盖单晶半导体插塞的牺牲层图案。 形成覆盖牺牲层图案和层间绝缘层的覆盖层，并且对覆盖层进行图案化以形成露出牺牲层图案的一部分的开口。 随后，选择性地去除牺牲层图案以在封盖层中形成空腔，并且形成平坦化的单晶半导体主体图案以填充空腔和开口。

公开(公告)号：US20060097328A1

公开(公告)日：2006-05-11

申请号：US11268138

申请日：2005-11-07

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

IPC分类号： H01L29/76

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

摘要翻译： 提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和该方法消除了具有垂直堆叠的上和下栅极图案的SRAM单元的结构特性所产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。 在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。 下部有源区域具有两个较低的单元栅极图案。 主体图案与半导体衬底平行设置。 形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。 着陆垫设置在下单元栅极图案之间。 形成节点图案以同时接触上单元格栅图案和下单元栅格图案。

公开(公告)号：US20050184292A1

公开(公告)日：2005-08-25

申请号：US11065750

申请日：2005-02-24

申请人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

发明人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

IPC分类号： H01L21/8244 ,  H01L27/108 ,  H01L27/11

CPC分类号： H01L27/1108 ,  H01L27/11

摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

摘要翻译： 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。

公开(公告)号：US20100275842A1

公开(公告)日：2010-11-04

申请号：US12659987

申请日：2010-03-26

申请人： Jae-Wan Park ,  You-Min Cha ,  Jae-Hong Ahn ,  Won-Seok Cho ,  Jae-Mork Park ,  Min-Jeong Hwang

发明人： Jae-Wan Park ,  You-Min Cha ,  Jae-Hong Ahn ,  Won-Seok Cho ,  Jae-Mork Park ,  Min-Jeong Hwang

IPC分类号： C23C16/00

CPC分类号： C23C14/243 ,  C23C14/044

摘要： Provided is an evaporating apparatus that deposits a deposition material onto a treatment object. The evaporating apparatus includes a base, a deposition source, and first and second correction units. The deposition source deposits the deposition material onto the treatment object. The base is disposed separately from the treatment object. The deposition source is placed on a surface of the base. The first and second correction units located between the deposition source and the treatment object. The first and second correction units are disposed on outer regions of the deposition source and face each other. Each of the first and second correction units rotates to control the thickness of a layer formed by the deposition material deposited on the treatment object.

摘要翻译： 提供了一种将沉积材料沉积到处理物体上的蒸发装置。 蒸发装置包括基座，沉积源以及第一和第二校正单元。 沉积源将沉积材料沉积到处理对象上。 基座与治疗对象分开设置。 沉积源放置在基底的表面上。 位于沉积源和处理对象之间的第一和第二校正单元。 第一和第二校正单元设置在沉积源的外部区域上并且彼此面对。 第一和第二校正单元中的每一个旋转以控制由沉积在处理对象上的沉积材料形成的层的厚度。

公开(公告)号：US08512473B2

公开(公告)日：2013-08-20

申请号：US12881759

申请日：2010-09-14

申请人： Jae-Mork Park ,  You-Min Cha ,  Won-Seok Cho ,  Jae-Hong Ahn ,  Min-Jeong Hwang

发明人： Jae-Mork Park ,  You-Min Cha ,  Won-Seok Cho ,  Jae-Hong Ahn ,  Min-Jeong Hwang

IPC分类号： C23C16/458 ,  H01L21/306 ,  C23F1/00 ,  C23C16/06 ,  C23C16/22

CPC分类号： H01L21/682 ,  C23C14/042 ,  H01L51/001 ,  H01L51/56

摘要： A substrate centering device for an organic material deposition system comprises: a plurality of substrate support holders configured to be reciprocally movable in a facing direction within an organic material deposition chamber and supporting both side portions of a substrate loaded by a robot; a substrate centering unit configured to be reciprocally movable at each of the substrate support holders and centering the substrate by guiding both side portions of the substrate; and a plurality of substrate clampers configured to be reciprocally movable in a vertical direction at each of the substrate support holders, and clamping the substrate that has been centered by the substrate centering unit.

摘要翻译： 一种用于有机材料沉积系统的基板定心装置，包括：多个基板支撑保持器，其构造成可在有机材料沉积室内面向相反方向往复运动，并支撑由机器人装载的基板的两侧部分; 基板定心单元，其构造成在每个基板支撑保持器处可往复运动，并且通过引导基板的两个侧部对准基板; 以及多个基板夹持器，其构造成在每个基板支撑保持器处在垂直方向上往复运动，并且夹持由基板定心单元居中的基板。

公开(公告)号：US08563378B2

公开(公告)日：2013-10-22

申请号：US13238104

申请日：2011-09-21

申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

IPC分类号： H01L21/336

CPC分类号： H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

摘要翻译： 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。