公开(公告)号：US07091598B2

公开(公告)日：2006-08-15

申请号：US10466300

申请日：2001-01-19

申请人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

发明人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

IPC分类号： H01L23/52

CPC分类号： G06F11/261 ,  G06F11/267 ,  G06F15/7867 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic circuit device has a high-density mount board, on which are disposed a microcomputer, a random access memory, a programmable device which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so as to be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device is simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized is simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

摘要翻译： 电子电路装置具有高密度安装板，微型计算机，随机存取存储器，作为由FPGA表示的可变逻辑电路的可编程装置以及可存储操作程序的电可重写非易失性存储器 的微机。 高密度安装板在底面上具有外部安装销，以与系统片上多芯片模块相同的方式安装在母板上。 通过在可编程器件上设置预期的逻辑功能，模拟由电子电路器件实现的基于硬件的功能。 通过将操作程序写入到非易失性存储器中，模拟要实现的基于软件的功能。 因此，该设备便于系统开发初期的调试，配置原型系统，有助于整个系统开发，原型制作和大规模生产的时间缩短。

公开(公告)号：US06609236B2

公开(公告)日：2003-08-19

申请号：US09964615

申请日：2001-09-28

申请人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G06F945

CPC分类号： G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

公开(公告)号：US06377267B1

公开(公告)日：2002-04-23

申请号：US09593496

申请日：2000-06-14

申请人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

发明人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

IPC分类号： G06F1300

CPC分类号： G06F3/14 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/127

摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。

公开(公告)号：US06246629B1

公开(公告)日：2001-06-12

申请号：US09551878

申请日：2000-04-18

申请人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G11C800

CPC分类号： G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

摘要翻译： 使用具有预先生成并存储在数据库中的多个I / O线，传输电路模块和逻辑库的存储器芯来设计半导体IC器件。 存储器核心和逻辑电路被布置成使得它们的I / O线沿相同的方向延伸。 在存储器芯的I / O线和逻辑电路的I / O线之间设置包括多级开关组的传输电路。 形成开关组的各级的开关形成在存储器芯的I / O线和逻辑电路的I / O线之间。 当开关组的一级或少量阶段被接通时，存储器芯的I / O线和逻辑电路的I / O线导通，从而形成期望的转移模式。 存储器芯由诸如放大器模块，存储体模块和电源模块的功能模块的组合构成。 在银行模块中布置了彼此独立操作的行系统电路和沿位线方向延伸的多个I / O线。

公开(公告)号：US06222563B1

公开(公告)日：2001-04-24

申请号：US09327355

申请日：1999-06-08

申请人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

发明人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

IPC分类号： G06F15167

CPC分类号： G06F3/14 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/127

摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。

公开(公告)号：US6069834A

公开(公告)日：2000-05-30

申请号：US813900

申请日：1997-03-07

申请人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G06F17/50 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C8/12 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

公开(公告)号：US5917496A

公开(公告)日：1999-06-29

申请号：US59397

申请日：1998-04-14

申请人： Ryo Fujita ,  Mitsuru Soga ,  Yasushi Fukunaga ,  Takehiko Nishida

发明人： Ryo Fujita ,  Mitsuru Soga ,  Yasushi Fukunaga ,  Takehiko Nishida

IPC分类号： G09G5/397 ,  G06T1/60 ,  G06T11/00 ,  G06T15/00 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399

CPC分类号： G06T15/005 ,  G06T1/60 ,  G09G5/393 ,  G09G5/395

摘要： The present invention relates to a three-dimensional graphic display apparatus for performing a hidden surface removal and color blending, and particularly to a configuration of a special purpose memory for graphics and a configuration of a graphic display apparatus using the special purpose memory. The special purpose memory for graphics according to the present invention comprises a memory cell for holding intensity information (RGB) and window information about each pixel therein, an XY coordinate converter for converting XY coordinates of a pixel to be written to a memory address, an intensity blending processor, and hidden-surface removal and window comparators, all of which are formed on the same chip.

摘要翻译： 本发明涉及一种用于执行隐藏表面去除和颜色混合的三维图形显示装置，特别涉及用于图形的专用存储器和使用专用存储器的图形显示装置的配置的配置。 根据本发明的用于图形的专用存储器包括用于保持强度信息（RGB）和关于其每个像素的窗口信息的存储单元，用于将要写入的像素的XY坐标转换为存储器地址的XY坐标转换器， 强度混合处理器和隐藏表面去除和窗口比较器，它们都形成在同一个芯片上。

公开(公告)号：US5673374A

公开(公告)日：1997-09-30

申请号：US53371

申请日：1993-04-28

申请人： Toru Sakaibara ,  Toshiyuki Kuwana ,  Ryo Fujita

发明人： Toru Sakaibara ,  Toshiyuki Kuwana ,  Ryo Fujita

IPC分类号： G06T11/20 ,  G06T15/02 ,  G06T15/04 ,  G06T15/80 ,  G06T15/50

CPC分类号： G06T15/506

摘要： Intensities of light reflected from a surface of an object to be displayed are calculated as to values of an ambient light reflection component, a diffuse light reflection component, and a specular reflection component. Judgement is made as whether the calculated value of the specular reflection component exceed a predetermined value. Texture data are blended with a sum of the calculated ambient light reflection component value and the calculated diffuse light reflection component value. If it is judged that the calculated specular reflection component value exceeds the predetermined value, the specular reflection component value is added to the blended value of the texture data with the sum of the calculated ambient light reflection component value and the calculated diffuse light reflection component value.

摘要翻译： 根据环境光反射分量，漫反射光反射分量和镜面反射分量的值来计算从待显示对象的表面反射的光的强度。 判断镜面反射分量的计算值是否超过预定值。 将纹理数据与所计算的环境光反射分量值和计算出的漫射光反射分量值的和进行混合。 如果判断出所计算的镜面反射分量值超过预定值，则将该反射分量值与计算出的环境光反射分量值和计算出的漫射光反射分量值之和相加到纹理数据的混合值 。

公开(公告)号：US5519449A

公开(公告)日：1996-05-21

申请号：US945937

申请日：1992-09-17

申请人： Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

发明人： Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

IPC分类号： G06T1/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/399 ,  H04N5/262 ,  H04N7/26 ,  H04N7/50 ,  H04N9/74

CPC分类号： G09G5/39 ,  G06T1/20 ,  H04N19/42 ,  H04N19/61 ,  H04N5/2624 ,  G09G2340/125 ,  G09G2360/123 ,  G09G5/36 ,  G09G5/399

摘要： An image composing and displaying apparatus includes frame memory constituent elements of an identical structure, a video input portion, a video output portion, a controller for selecting connection of each element to the video input or output portion, and an image drawing portion for reading and writing video data from and in the memory elements. The memory elements can be used for the input and output operations and hence the size thereof can be easily expanded; moreover, the numbers of the elements respectively connected to the video input and output portion can be adaptively varied.

摘要翻译： 图像合成显示装置包括具有相同结构的帧存储器组成元件，视频输入部分，视频输出部分，用于选择每个元素与视频输入或输出部分的连接的控制器，以及用于读取和/ 从存储器元件中写入视频数据。 存储元件可用于输入和输出操作，因此其尺寸可以容易地扩展; 此外，分别连接到视频输入和输出部分的元件的数量可以自适应地变化。

公开(公告)号：US5371839A

公开(公告)日：1994-12-06

申请号：US634818

申请日：1991-01-02

申请人： Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Isao Yasuda ,  Takeshi Kato

发明人： Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Isao Yasuda ,  Takeshi Kato

IPC分类号： G06T15/80 ,  G06F15/16

CPC分类号： G06T15/80

摘要： A rendering processor having a plurality of DDA control circuits such that in each DDA circuit, the coordinates of source and destination images and gradation values are computed. Depending on the computation result, source and destination data to the raster arithmetic unit are generated so as to control the raster arithmetic unit, which enables a plurality of pixels to be generated and to be written in the memory during a memory access.

摘要翻译： 具有多个DDA控制电路的渲染处理器，使得在每个DDA电路中，计算源和目的地图像的坐标以及灰度值。 根据计算结果，生成到光栅运算单元的源和目的地数据，以便控制光栅运算单元，这使得能够在存储器访问期间生成多个像素并将其写入存储器。