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    Programmable logic device architectures and methods for implementing logic in those architectures
    41.
    发明授权
    Programmable logic device architectures and methods for implementing logic in those architectures 有权
    可编程逻辑器件架构和方法，用于在这些架构中实现逻辑

    公开(公告)号：US07716623B1

    公开(公告)日：2010-05-11

    申请号：US12580038

    申请日：2009-10-15

    申请人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    发明人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    IPC分类号： H03K17/693

    CPC分类号： H03K19/17736

    摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

    摘要翻译： 可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LAB）“的群集在一起的逻辑元件（”LE“）。 为了节省面积，与现有技术相比，减少或消除了局部反馈资源（用于将LAB中的LE的输出反馈到LAB中的LE的输入）。 因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须通过LAB的通用输入路由资源路由，所以保存那些 资源。 例如，通过在确定在LAB中一起实现哪些逻辑功能时，更重要的是找到具有共同输入的逻辑功能。

    Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design Software
    42.
    发明申请
    Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design Software 审中-公开
    并联集成电路计算机辅助设计软件的装置与方法

    公开(公告)号：US20100070979A1

    公开(公告)日：2010-03-18

    申请号：US12545224

    申请日：2009-08-21

    申请人： Adrian Ludwin ,  Vaughn Betz ,  Ketan Padalia

    发明人： Adrian Ludwin ,  Vaughn Betz ,  Ketan Padalia

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4881 ,  G06F2209/483 ,  G06F2209/484

    摘要： A system for parallelizing software in computer-aided design (CAD) software for logic design includes a computer. The computer is configured to identify dependencies among a set of tasks. The computer is also configured to perform the set of tasks in parallel such that a solution of a problem is identical to a solution produced by performing the set of tasks serially.

    摘要翻译： 用于并行化用于逻辑设计的计算机辅助设计（CAD）软件中的软件的系统包括计算机。 计算机被配置为识别一组任务之间的依赖关系。 计算机还被配置为并行地执行一组任务，使得问题的解决方案与通过一致地执行该任务所产生的解决方案相同。

    Systems and methods for reducing static and total power consumption in a programmable logic device
    43.
    发明授权
    Systems and methods for reducing static and total power consumption in a programmable logic device 失效
    用于减少可编程逻辑器件中的静态和总功耗的系统和方法

    公开(公告)号：US07467314B2

    公开(公告)日：2008-12-16

    申请号：US11642287

    申请日：2006-12-19

    申请人： David Mendel ,  Vaughn Betz

    发明人： David Mendel ,  Vaughn Betz

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/32

    摘要： A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

    摘要翻译： 提供了一种用于降低可编程逻辑器件（PLD）中功耗的方法和系统。 在可编程逻辑器件的技术映射，路由和后续周期期间，优选地可以连续地考虑功率消耗作为电路设计中的一个因素来降低功耗。

    Methods for designing integrated circuits
    44.
    发明授权
    Methods for designing integrated circuits 有权
    集成电路设计方法

    公开(公告)号：US07441208B1

    公开(公告)日：2008-10-21

    申请号：US11225919

    申请日：2005-09-13

    申请人： Ketan Padalia ,  Vaughn Betz ,  Vadim Gouterman

    发明人： Ketan Padalia ,  Vaughn Betz ,  Vadim Gouterman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： The process of designing an integrated circuit (“IC”) to implement a generalized circuit design includes a signoff between a front-end part of the process and a back-end part of the process. This signoff preferably takes place after at least some global routing has been done for the IC implementation, but before all final detailed routing is done for that implementation.

    摘要翻译： 设计集成电路（“IC”）以实现广义电路设计的过程包括过程的前端部分与过程的后端部分之间的签名。 这种签名优选在对IC实现进行至少一些全局路由之后，但在为该实现完成所有最终详细路由之前进行。

    Apparatus and methods for parallelizing integrated circuit computer-aided design software
    47.
    发明申请
    Apparatus and methods for parallelizing integrated circuit computer-aided design software 审中-公开
    用于并行集成电路计算机辅助设计软件的装置和方法

    公开(公告)号：US20070192766A1

    公开(公告)日：2007-08-16

    申请号：US11392215

    申请日：2006-03-29

    申请人： Ketan Padalia ,  Adrian Ludwin ,  Vaughn Betz ,  Ryan Fung

    发明人： Ketan Padalia ,  Adrian Ludwin ,  Vaughn Betz ,  Ryan Fung

    IPC分类号： G06F9/46

    CPC分类号： G06F8/45 ,  G06F17/5054

    摘要： A system for providing parallelization in computer aided design (CAD) software includes a computer. The computer is configured to identify a set of tasks having local independence, and assign each task in the set of tasks to be performed in parallel. The computer is further configured to perform each task in the set of tasks.

    摘要翻译： 用于在计算机辅助设计（CAD）软件中提供并行化的系统包括计算机。 计算机被配置为识别具有本地独立性的一组任务，并且将要并行执行的任务集中的每个任务分配。 计算机还被配置为在该组任务中执行每个任务。

    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability
    48.
    发明授权
    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability 有权

    公开(公告)号：US07254789B1

    公开(公告)日：2007-08-07

    申请号：US11002977

    申请日：2004-12-01

    申请人： Ryan Fung ,  Vaughn Betz

    发明人： Ryan Fung ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/5045

    摘要： Logic designs are optimized to satisfy long-path and short-path timing constraints for multiple process/operating condition corners. A path-based compilation phase determines an implementation for logic design paths, in part, by monitoring a set of paths that are important from a timing perspective and evaluating the timing performance of the set of monitored paths at one or more timing corners. A timing-analysis-based compilation phase determines transformations for converting sets of timing values from one timing corner to another timing corner. The compilation phase transforms timing delay values from one timing corner to another to facilitate analysis of timing performance at different corners. Timing slack values produced by analysis are transformed to map them from one timing corner to another. The transformed timing slack values from multiple corners are amalgamated. The amalgamated timing slack values are used by a compilation phase (that potentially only understands a single corner) to optimize a logic design for multiple corners.